diff options
| author | Diana Z <dzigterman@chromium.org> | 2021-12-16 16:19:51 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-12-20 18:56:12 +0000 |
| commit | df72b348479673ab2ea2db1fff005426df5c52c1 (patch) | |
| tree | c006abad9961e669e840c5c261a8080d34f0d178 /baseboard/guybrush | |
| parent | 8637afa2123785ae0e3ffc4a35de273c79c304c4 (diff) | |
| download | chrome-ec-df72b348479673ab2ea2db1fff005426df5c52c1.tar.gz | |
Guybrush: Restore TCPC I/O pins after TCPC reset
Right now, we may reset the TCPC during runtime in order to get it out
of dead battery mode so that we may control the sink enable pin.
However, when the TCPC is reset then the I/O ports on it will need to be
restored in order for the Type-A ports to work correctly.
The Type-C related I/O pins should be irrelevant since the port will
be going through Error Recovery after the reset, and will be set there.
BRANCH=None
BUG=b:210802721
TEST=on dewatt, confirm A port works on a boot when the battery is
being brought out of cutoff and C0 gets reset
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I5ac57c2bed5235c94446e51975c793abcfbffb7e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3345994
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: Rob Barnes <robbarnes@google.com>
Diffstat (limited to 'baseboard/guybrush')
| -rw-r--r-- | baseboard/guybrush/baseboard.c | 25 |
1 files changed, 22 insertions, 3 deletions
diff --git a/baseboard/guybrush/baseboard.c b/baseboard/guybrush/baseboard.c index 26f212e986..447365a313 100644 --- a/baseboard/guybrush/baseboard.c +++ b/baseboard/guybrush/baseboard.c @@ -611,14 +611,22 @@ void tcpc_alert_event(enum gpio_signal signal) static void reset_nct38xx_port(int port) { enum gpio_signal reset_gpio_l; + int a_vbus, a_limit_sdp, a1_retimer_en; - if (port == USBC_PORT_C0) + /* Save type-A GPIO values to restore after reset */ + if (port == USBC_PORT_C0) { reset_gpio_l = GPIO_USB_C0_TCPC_RST_L; - else if (port == USBC_PORT_C1) + ioex_get_level(IOEX_EN_PP5000_USB_A0_VBUS, &a_vbus); + ioex_get_level(IOEX_USB_A0_LIMIT_SDP, &a_limit_sdp); + } else if (port == USBC_PORT_C1) { reset_gpio_l = GPIO_USB_C1_TCPC_RST_L; - else + ioex_get_level(IOEX_EN_PP5000_USB_A1_VBUS_DB, &a_vbus); + ioex_get_level(IOEX_USB_A1_LIMIT_SDP_DB, &a_limit_sdp); + ioex_get_level(IOEX_USB_A1_RETIMER_EN, &a1_retimer_en); + } else { /* Invalid port: do nothing */ return; + } gpio_set_level(reset_gpio_l, 0); msleep(NCT38XX_RESET_HOLD_DELAY_MS); @@ -626,6 +634,17 @@ static void reset_nct38xx_port(int port) nct38xx_reset_notify(port); if (NCT3807_RESET_POST_DELAY_MS != 0) msleep(NCT3807_RESET_POST_DELAY_MS); + + /* Re-init ioex after resetting the TCPC */ + ioex_init(port); + if (port == USBC_PORT_C0) { + ioex_set_level(IOEX_EN_PP5000_USB_A0_VBUS, a_vbus); + ioex_set_level(IOEX_USB_A0_LIMIT_SDP, a_limit_sdp); + } else { + ioex_set_level(IOEX_EN_PP5000_USB_A1_VBUS_DB, a_vbus); + ioex_set_level(IOEX_USB_A1_LIMIT_SDP_DB, a_limit_sdp); + ioex_set_level(IOEX_USB_A1_RETIMER_EN, a1_retimer_en); + } } |