ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ish

In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.

This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.

The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.

BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>

7 files changed, 0 insertions, 1671 deletions

diff --git a/baseboard/guybrush/base_fw_config.h b/baseboard/guybrush/base_fw_config.h
deleted file mode 100644
index 2eea7a158f..0000000000
--- a/baseboard/guybrush/base_fw_config.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef _GUYBRUSH_BASE_FW_CONFIG__H_
-#define _GUYBRUSH_BASE_FW_CONFIG__H_
-
-#define UNINITIALIZED_FW_CONFIG 0xFFFFFFFF
-
-#include <stdbool.h>
-#include <stdint.h>
-
-/*
- * Takes a bit offset and bit width and returns the fw_config field at that
- * offset and width. Returns -1 if an error occurs.
- */
-int get_fw_config_field(uint8_t offset, uint8_t width);
-
-/*
- * Each Guybrush board variant will define a board specific fw_config schema.
- * Below is the schema agnostic interface for fw_config fields.
- * Fields that are not applicable outside a specific Guybrush variant do not
- * need to be included here.
- */
-
-enum board_usb_a1_retimer {
-	USB_A1_RETIMER_UNKNOWN,
-	USB_A1_RETIMER_PS8811,
-	USB_A1_RETIMER_ANX7491
-};
-
-enum board_usb_c1_mux {
-	USB_C1_MUX_UNKNOWN,
-	USB_C1_MUX_PS8818,
-	USB_C1_MUX_ANX7451
-};
-
-enum board_form_factor {
-	FORM_FACTOR_UNKNOWN,
-	FORM_FACTOR_CLAMSHELL,
-	FORM_FACTOR_CONVERTIBLE
-};
-
-bool board_has_kblight(void);
-enum board_usb_a1_retimer board_get_usb_a1_retimer(void);
-enum board_usb_c1_mux board_get_usb_c1_mux(void);
-enum board_form_factor board_get_form_factor(void);
-bool board_is_convertible(void);
-
-#endif /* _GUYBRUSH_BASE_FW_CONFIG__H_ */
diff --git a/baseboard/guybrush/base_gpio.inc b/baseboard/guybrush/base_gpio.inc
deleted file mode 100644
index 259ccd9286..0000000000
--- a/baseboard/guybrush/base_gpio.inc
+++ /dev/null
@@ -1,150 +0,0 @@
-/* -*- mode:c -*-
- *
- * Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* GSC Signals */
-GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)	/* Write Protect Enabled */
-GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_ODR_HIGH)						/* Case Closed Debug Mode */
-GPIO(EC_GSC_PACKET_MODE,	PIN(B, 1), GPIO_OUT_LOW)						/* GSC Packet Mode */
-ALTERNATE(			PIN_MASK(6, BIT(4) | BIT(5)), 0,		MODULE_UART, 0) 	/* UART_EC_TX_GSC_DBG_RX_R, UART_GSC_DBG_TX_EC_RX_R */
-
-/* Power Signals */
-GPIO_INT(MECH_PWR_BTN_ODL,	PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, 	power_button_interrupt)	/* Mechanical Power Button */
-GPIO_INT(EC_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH, 			power_button_interrupt) /* Power Button */
-GPIO_INT(SLP_S3_L,		PIN(6, 1), GPIO_INT_BOTH,			baseboard_en_pwr_s0)	/* Sleep S3 */
-GPIO_INT(SLP_S5_L,		PIN(7, 2), GPIO_INT_BOTH,			power_signal_interrupt) /* Sleep S5 */
-GPIO_INT(SLP_S3_S0I3_L,		PIN(7, 4), GPIO_INT_BOTH,			power_signal_interrupt) /* Sleep S0ix */
-GPIO_INT(PG_PWR_S5,		PIN(C, 0), GPIO_INT_BOTH,			baseboard_en_pwr_s0)	/* S5 Power OK */
-GPIO_INT(PG_PCORE_S0_R_OD,	PIN(B, 6), GPIO_INT_BOTH, 			power_signal_interrupt) /* S0 Power OK */
-GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)	/* AC Power Present */
-GPIO_INT(EC_PCORE_INT_ODL,	PIN(F, 0), GPIO_INT_BOTH | GPIO_PULL_UP,	power_signal_interrupt)	/* Power Core Interrupt */
-GPIO_INT(PG_GROUPC_S0_OD,	PIN(A, 3), GPIO_INT_BOTH, 			baseboard_en_pwr_pcore_s0)	/* Power Group C S0 */
-GPIO_INT(PG_LPDDR4X_S3_OD,	PIN(9, 5), GPIO_INT_BOTH, 			baseboard_en_pwr_pcore_s0)	/* Power Group LPDDR4 S3 */
-GPIO(EN_PWR_S5,			PIN(B, 7), GPIO_OUT_LOW)						/* Enable S5 Power */
-GPIO(EN_PWR_S0_R,		PIN(F, 1), GPIO_OUT_LOW)
-GPIO(EN_PWR_PCORE_S0_R,		PIN(E, 1), GPIO_OUT_LOW)
-ALTERNATE(/*MECH_PWR_BTN_ODL*/	PIN_MASK(D, BIT(2)), 0,				MODULE_PMU, 0)		/* PSL - Mechanical Power Button */
-ALTERNATE(/*LID_OPEN*/		PIN_MASK(0, BIT(2)), 0, 			MODULE_PMU, 0)		/* PSL - Lid Open */
-ALTERNATE(/*ACOK_OD*/		PIN_MASK(0, BIT(0)), 0,				MODULE_PMU, 0)		/* PSL - AC Power Present */
-
-/* SOC Signals */
-GPIO(EC_ENTERING_RW,		PIN(6, 6), GPIO_OUT_LOW) 						/* Tell SOC we entered RW */
-GPIO(EC_SYS_RST_L,		PIN(7, 6), GPIO_ODR_HIGH)						/* Cold Reset SOC */
-GPIO(EC_SOC_RSMRST_L,		PIN(C, 5), GPIO_OUT_LOW)						/* Resume Reset SOC */
-GPIO(EC_CLR_CMOS,		PIN(A, 1), GPIO_OUT_LOW)						/* Clear SOC CMOS */
-GPIO(EC_MEM_EVENT,		PIN(A, 5), GPIO_OUT_LOW)						/* Memory Thermal Event to SOC*/
-GPIO(EC_SOC_PWR_BTN_L,		PIN(6, 3), GPIO_OUT_HIGH)						/* Power Button to SOC */
-GPIO(EC_SOC_PWR_GOOD,		PIN(D, 3), GPIO_OUT_LOW)						/* Power Good to SOC */
-GPIO(EC_SOC_WAKE_L,		PIN(0, 3), GPIO_OUT_HIGH)						/* Wake SOC */
-GPIO(EC_SOC_INT_L,		PIN(8, 3), GPIO_OUT_HIGH)						/* Matrix Keyboard Protocol Event to SOC */
-GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)						/* Force SOC into HTC-active state */
-GPIO(SOC_ALERT_EC_L,		PIN(E, 2), GPIO_INPUT)							/* Sideband-Temperature Iterrupt */
-GPIO(SOC_THERMTRIP_ODL, 	PIN(E, 5), GPIO_INPUT)							/* Temperature Trip Sensor */
-
-/* USB Signals */
-GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(C, 7), GPIO_INT_FALLING,			tcpc_alert_event)
-GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(7, 5), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(D, 4), GPIO_INT_FALLING,			ppc_interrupt)
-GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO_INT(USB_C1_BC12_INT_ODL, 	PIN(9, 6), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
-GPIO(USB_C0_C1_FAULT_ODL,	PIN(7, 3), GPIO_ODR_HIGH)						/* C0/C1 Fault to SOC */
-GPIO(USB_C0_TCPC_RST_L,		PIN(3, 4), GPIO_OUT_HIGH)						/* C0 TCPC Reset */
-GPIO(USB_C1_TCPC_RST_L,		PIN(3, 7), GPIO_OUT_HIGH)						/* C1 TCPC Reset */
-GPIO(USB_C0_HPD,		PIN(F, 5), GPIO_OUT_LOW)						/* C0 DP Hotplug Detect */
-GPIO(USB_C1_HPD,		PIN(F, 4), GPIO_OUT_LOW)						/* C1 DP Hotplug Detect */
-
-/* Sensor Signals */
-GPIO(3AXIS_INT_L,		PIN(A, 2), GPIO_INPUT | GPIO_PULL_DOWN)					/* 3 Axis Accel */
-GPIO_INT(LID_OPEN,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)		/* Lid Open */
-GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 7), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)	/* Volume Down */
-GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, 	button_interrupt)	/* Volume Up */
-GPIO(EC_BATT_PRES_ODL,		PIN(9, 4), GPIO_INPUT)							/* Battery Present */
-ALTERNATE(/*TEMP_SOC|CHRG|MEM*/	PIN_MASK(4, BIT(3) | BIT(4) | BIT(5)), 0, 	MODULE_ADC, 0)		/* SOC, Charger and Memory Temperature */
-ALTERNATE(			PIN_MASK(4, BIT(1) | BIT(2)), 0,		MODULE_ADC, 0)		/* EC_ADC_CORE_IMON1, EC_ADC_SOC_IMON2 */
-
-/* LED Signals */
-GPIO(EC_DISABLE_DISP_BL,	PIN(A, 6), GPIO_OUT_HIGH)						/* Disable Display Backlight */
-
-/* Fan Signals */
-ALTERNATE(			PIN_MASK(C, BIT(3)), 0, 			MODULE_PWM, 0)		/* EC_FAN_PWM - Fan PWM */
-ALTERNATE(			PIN_MASK(4, BIT(0)), 0, 			MODULE_PWM, 0)		/* EC_FAN_SPEED - Fan Speed */
-
-/* I2C Signals -- i2c pins need to be exposed as GPIO for bit banging, even though set to alternate mode below */
-GPIO(EC_I2C_USB_A0_C0_SCL,	PIN(B, 5), GPIO_INPUT)
-GPIO(EC_I2C_USB_A0_C0_SDA,	PIN(B, 4), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SCL,	PIN(9, 0), GPIO_INPUT)
-GPIO(EC_I2C_USB_A1_C1_SDA,	PIN(8, 7), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SCL,		PIN(9, 2), GPIO_INPUT)
-GPIO(EC_I2C_BATT_SDA,		PIN(9, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_MUX_SCL,	PIN(D, 1), GPIO_INPUT)
-GPIO(EC_I2C_USBC_MUX_SDA,	PIN(D, 0), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SCL,		PIN(F, 3), GPIO_INPUT)
-GPIO(EC_I2C_POWER_SDA,		PIN(F, 2), GPIO_INPUT)
-GPIO(EC_I2C_CBI_SCL,		PIN(3, 3), GPIO_INPUT)
-GPIO(EC_I2C_CBI_SDA,		PIN(3, 6), GPIO_INPUT)
-GPIO(EC_I2C_SENSOR_SCL,		PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SENSOR_SDA,		PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V)
-GPIO(EC_I2C_SOC_SIC,		PIN(B, 3), GPIO_INPUT)
-GPIO(EC_I2C_SOC_SID,		PIN(B, 2), GPIO_INPUT)
-
-ALTERNATE(			PIN_MASK(B, BIT(4) | BIT(5)), 0, 		MODULE_I2C, 0)		/* I2C0 */
-ALTERNATE(			PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, 	MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
-ALTERNATE(			PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)					/* I2C1 SDA */
-ALTERNATE(			PIN_MASK(D, BIT(0) | BIT(1)), 0, 		MODULE_I2C, 0)		/* I2C3 */
-ALTERNATE(			PIN_MASK(F, BIT(2) | BIT(3)), 0, 		MODULE_I2C, 0)		/* I2C4 */
-ALTERNATE(			PIN_MASK(3, BIT(3) | BIT(6)), 0, 		MODULE_I2C, 0)		/* I2C5 */
-ALTERNATE(			PIN_MASK(E, BIT(3) | BIT(4)), 0, 		MODULE_I2C, 0)		/* I2C6 */
-ALTERNATE(			PIN_MASK(B, BIT(2) | BIT(3)), 0, 		MODULE_I2C, 0)		/* I2C7 */
-
-/* Keyboard Signals */
-GPIO(EN_KB_BL, 			PIN(9, 7), GPIO_OUT_HIGH)						/* Enable Keyboard Backlight */
-ALTERNATE(/*PWM_KB_BL*/ 	PIN_MASK(C, BIT(2)), 0, 			MODULE_PWM, 0)		/* Keyboard Backlight Level */
-ALTERNATE(/*KSI_00-01*/		PIN_MASK(3, BIT(0) | BIT(1)), 0, 		MODULE_KEYBOARD_SCAN, GPIO_INPUT)
-ALTERNATE(/*KSI_02-07*/		PIN_MASK(2, GENMASK(7, 2)), 0, 			MODULE_KEYBOARD_SCAN, GPIO_INPUT)
-ALTERNATE(/*KSO_00-01*/		PIN_MASK(2, BIT(0) | BIT(1)), 0, 		MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)
-GPIO(EC_KSO_02_INV, 		PIN(1, 7), GPIO_OUT_LOW)						/* KSO_02 inverted */
-ALTERNATE(/*KSO_03-09*/		PIN_MASK(1, GENMASK(6, 0)), 0,			MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)
-ALTERNATE(/*KSO_10-13*/		PIN_MASK(0, GENMASK(7, 4)), 0, 			MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)
-ALTERNATE(/*KSO_14*/		PIN_MASK(8, BIT(2)), 0, 			MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)
-
-/* b/186135022: Pull eSPI RST# high to disable */
-GPIO(EC_ESPI_RST_L,		PIN(5, 4), GPIO_PULL_UP)
-
-#if 0
-/*
- * SOC eSPI Bus
- * These signals do not need to be explicitly configured.
- * Leaving here so all signals are documented.
- */
-GPIO(ESPI_SOC_CLK,		PIN(5, 5), GPIO_DEFAULT)
-GPIO(ESPI_SOC_CS_EC_L,		PIN(5, 3), GPIO_DEFAULT)
-GPIO(ESPI_SOC_D0_EC,		PIN(4, 6), GPIO_DEFAULT)
-GPIO(ESPI_SOC_D1_EC,		PIN(4, 7), GPIO_DEFAULT)
-GPIO(ESPI_SOC_D2_EC,		PIN(5, 1), GPIO_DEFAULT)
-GPIO(ESPI_SOC_D3_EC,		PIN(5, 2), GPIO_DEFAULT)
-GPIO(ESPI_EC_ALERT_SOC_L,	PIN(5, 7), GPIO_DEFAULT)
-#endif
-
-/* TCPC C0 */
-IOEX(USB_C0_TCPC_FASTSW_CTL_EN, EXPIN(USBC_PORT_C0, 0, 4), GPIO_OUT_LOW)
-IOEX(USB_C0_PPC_EN_L,		EXPIN(USBC_PORT_C0, 1, 0), GPIO_OUT_LOW)
-IOEX(USB_C0_PPC_ILIM_3A_EN,	EXPIN(USBC_PORT_C0, 1, 1), GPIO_OUT_LOW)
-IOEX_INT(USB_C0_SBU_FAULT_ODL,	EXPIN(USBC_PORT_C0, 1, 2), GPIO_INT_FALLING,	sbu_fault_interrupt)
-IOEX(EN_PP5000_USB_A0_VBUS,	EXPIN(USBC_PORT_C0, 1, 5), GPIO_OUT_LOW)
-IOEX(USB_A0_LIMIT_SDP,		EXPIN(USBC_PORT_C0, 1, 6), GPIO_OUT_LOW)
-IOEX(USB_C0_SBU_FLIP,		EXPIN(USBC_PORT_C0, 1, 7), GPIO_OUT_LOW)
-
-/* TCPC C1 */
-IOEX(USB_A1_RETIMER_EN,		EXPIN(USBC_PORT_C1, 0, 0), GPIO_OUT_LOW)
-IOEX(USB_A1_RETIMER_RST,	EXPIN(USBC_PORT_C1, 0, 1), GPIO_OUT_LOW)
-IOEX(USB_C1_IN_HPD,		EXPIN(USBC_PORT_C1, 0, 3), GPIO_OUT_LOW)
-IOEX(USB_C1_TCPC_FASTSW_CTL_EN, EXPIN(USBC_PORT_C1, 0, 4), GPIO_OUT_LOW)
-IOEX(USB_C1_PPC_EN_L,		EXPIN(USBC_PORT_C1, 1, 0), GPIO_OUT_LOW)
-IOEX(USB_C1_PPC_ILIM_3A_EN,	EXPIN(USBC_PORT_C1, 1, 1), GPIO_OUT_LOW)
-IOEX_INT(USB_C1_SBU_FAULT_ODL,	EXPIN(USBC_PORT_C1, 1, 2), GPIO_INT_FALLING,	sbu_fault_interrupt)
-IOEX(EN_PP5000_USB_A1_VBUS_DB,	EXPIN(USBC_PORT_C1, 1, 5), GPIO_OUT_LOW)
-IOEX(USB_A1_LIMIT_SDP_DB,	EXPIN(USBC_PORT_C1, 1, 6), GPIO_OUT_LOW)
diff --git a/baseboard/guybrush/baseboard.c b/baseboard/guybrush/baseboard.c
deleted file mode 100644
index 344ea459de..0000000000
--- a/baseboard/guybrush/baseboard.c
+++ /dev/null
@@ -1,894 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Guybrush family-specific configuration */
-
-#include "cros_board_info.h"
-#include "base_fw_config.h"
-#include "battery_fuel_gauge.h"
-#include "charge_manager.h"
-#include "charge_ramp.h"
-#include "charge_state_v2.h"
-#include "charge_state.h"
-#include "charger.h"
-#include "chip/npcx/ps2_chip.h"
-#include "chip/npcx/pwm_chip.h"
-#include "chipset.h"
-#include "driver/ppc/aoz1380.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/retimer/anx7491.h"
-#include "driver/retimer/ps8811.h"
-#include "driver/retimer/ps8818.h"
-#include "driver/tcpm/nct38xx.h"
-#include "driver/usb_mux/anx7451.h"
-#include "driver/usb_mux/amd_fp6.h"
-#include "fan.h"
-#include "fan_chip.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "ioexpander.h"
-#include "isl9241.h"
-#include "keyboard_scan.h"
-#include "nct38xx.h"
-#include "pi3usb9201.h"
-#include "power.h"
-#include "pwm.h"
-#include "usb_mux.h"
-#include "usb_pd_tcpm.h"
-#include "usbc_ppc.h"
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-static void reset_nct38xx_port(int port);
-
-/* Wake Sources */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
-
-/* Power Signal Input List */
-const struct power_signal_info power_signal_list[] = {
-	[X86_SLP_S0_N] = {
-		.gpio = GPIO_PCH_SLP_S0_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S0_DEASSERTED",
-	},
-	[X86_SLP_S3_N] = {
-		.gpio = GPIO_PCH_SLP_S3_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S3_DEASSERTED",
-	},
-	[X86_SLP_S5_N] = {
-		.gpio = GPIO_PCH_SLP_S5_L,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "SLP_S5_DEASSERTED",
-	},
-	[X86_S0_PGOOD] = {
-		.gpio = GPIO_S0_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S0_PGOOD",
-	},
-	[X86_S5_PGOOD] = {
-		.gpio = GPIO_S5_PGOOD,
-		.flags = POWER_SIGNAL_ACTIVE_HIGH,
-		.name = "S5_PGOOD",
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
-
-const struct i2c_port_t i2c_ports[] = {
-	{
-		.name = "tcpc0",
-		.port = I2C_PORT_TCPC0,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_A0_C0_SCL,
-		.sda = GPIO_EC_I2C_USB_A0_C0_SDA,
-	},
-	{
-		.name = "tcpc1",
-		.port = I2C_PORT_TCPC1,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USB_A1_C1_SCL,
-		.sda = GPIO_EC_I2C_USB_A1_C1_SDA,
-	},
-	{
-		.name = "battery",
-		.port = I2C_PORT_BATTERY,
-		.kbps = 100,
-		.scl = GPIO_EC_I2C_BATT_SCL,
-		.sda = GPIO_EC_I2C_BATT_SDA,
-	},
-	{
-		.name = "usb_mux",
-		.port = I2C_PORT_USB_MUX,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_USBC_MUX_SCL,
-		.sda = GPIO_EC_I2C_USBC_MUX_SDA,
-	},
-	{
-		.name = "charger",
-		.port = I2C_PORT_CHARGER,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_POWER_SCL,
-		.sda = GPIO_EC_I2C_POWER_SDA,
-	},
-	{
-		.name = "eeprom",
-		.port = I2C_PORT_EEPROM,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_CBI_SCL,
-		.sda = GPIO_EC_I2C_CBI_SDA,
-	},
-	{
-		.name = "sensor",
-		.port = I2C_PORT_SENSOR,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_SENSOR_SCL,
-		.sda = GPIO_EC_I2C_SENSOR_SDA,
-	},
-	{
-		.name = "soc_thermal",
-		.port = I2C_PORT_THERMAL_AP,
-		.kbps = 400,
-		.scl = GPIO_EC_I2C_SOC_SIC,
-		.sda = GPIO_EC_I2C_SOC_SID,
-	},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-
-
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
-		.drv = &isl9241_drv,
-	},
-};
-
-const struct tcpc_config_t tcpc_config[] = {
-	[USBC_PORT_C0] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC0,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-	[USBC_PORT_C1] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_TCPC1,
-			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		},
-		.drv = &nct38xx_tcpm_drv,
-		.flags = TCPC_FLAGS_TCPCI_REV2_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
-
-const int usb_port_enable[USBA_PORT_COUNT] = {
-	IOEX_EN_PP5000_USB_A0_VBUS,
-	IOEX_EN_PP5000_USB_A1_VBUS_DB,
-};
-
-static void baseboard_interrupt_init(void)
-{
-	/* Enable Power Group interrupts. */
-	gpio_enable_interrupt(GPIO_PG_GROUPC_S0_OD);
-	gpio_enable_interrupt(GPIO_PG_LPDDR4X_S3_OD);
-
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
-
-	/* Enable BC 1.2 interrupts */
-	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
-	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
-
-	/* Enable SBU fault interrupts */
-	ioex_enable_interrupt(IOEX_USB_C0_SBU_FAULT_ODL);
-	ioex_enable_interrupt(IOEX_USB_C1_SBU_FAULT_ODL);
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_interrupt_init, HOOK_PRIO_INIT_I2C + 1);
-
-struct ppc_config_t ppc_chips[] = {
-	[USBC_PORT_C0] = {
-		/* Device does not talk I2C */
-		.drv = &aoz1380_drv
-	},
-
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = NX20P3483_ADDR1_FLAGS,
-		.drv = &nx20p348x_drv
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
-	[USBC_PORT_C0] = {
-		.i2c_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-
-	[USBC_PORT_C1] = {
-		.i2c_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
-
-/*
- * .init is not necessary here because it has nothing
- * to do. Primary mux will handle mux state so .get is
- * not needed as well. usb_mux.c can handle the situation
- * properly.
- */
-static int fsusb42umx_set_mux(const struct usb_mux*, mux_state_t, bool *);
-struct usb_mux_driver usbc0_sbu_mux_driver = {
-	.set = fsusb42umx_set_mux,
-};
-
-/*
- * Since FSUSB42UMX is not a i2c device, .i2c_port and
- * .i2c_addr_flags are not required here.
- */
-struct usb_mux usbc0_sbu_mux = {
-	.usb_port = USBC_PORT_C0,
-	.driver = &usbc0_sbu_mux_driver,
-};
-
-__overridable int board_c1_ps8818_mux_set(const struct usb_mux *me,
-					  mux_state_t mux_state)
-{
-	CPRINTSUSB("C1: PS8818 mux using default tuning");
-	return 0;
-}
-
-struct usb_mux usbc1_ps8818 = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.flags = USB_MUX_FLAG_RESETS_IN_G3,
-	.i2c_addr_flags = PS8818_I2C_ADDR_FLAGS,
-	.driver = &ps8818_usb_retimer_driver,
-	.board_set = &board_c1_ps8818_mux_set,
-};
-
-__overridable int board_c1_anx7451_mux_set(const struct usb_mux *me,
-					   mux_state_t mux_state)
-{
-	CPRINTSUSB("C1: ANX7451 mux using default tuning");
-	return 0;
-}
-
-struct usb_mux usbc1_anx7451 = {
-	.usb_port = USBC_PORT_C1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.flags = USB_MUX_FLAG_RESETS_IN_G3,
-	.i2c_addr_flags = ANX7491_I2C_ADDR3_FLAGS,
-	.driver = &anx7451_usb_mux_driver,
-	.board_set = &board_c1_anx7451_mux_set,
-};
-
-struct usb_mux usb_muxes[] = {
-	[USBC_PORT_C0] = {
-		.usb_port = USBC_PORT_C0,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = AMD_FP6_C0_MUX_I2C_ADDR,
-		.driver = &amd_fp6_usb_mux_driver,
-		.next_mux = &usbc0_sbu_mux,
-	},
-	[USBC_PORT_C1] = {
-		.usb_port = USBC_PORT_C1,
-		.i2c_port = I2C_PORT_USB_MUX,
-		.i2c_addr_flags = AMD_FP6_C4_MUX_I2C_ADDR,
-		.driver = &amd_fp6_usb_mux_driver,
-		/* .next_mux = filled in by setup_mux based on fw_config */
-	}
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
-
-struct ioexpander_config_t ioex_config[] = {
-	[USBC_PORT_C0] = {
-		.i2c_host_port = I2C_PORT_TCPC0,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-	},
-	[USBC_PORT_C1] = {
-		.i2c_host_port = I2C_PORT_TCPC1,
-		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
-		.drv = &nct38xx_ioexpander_drv,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(ioex_config) == USBC_PORT_COUNT);
-BUILD_ASSERT(CONFIG_IO_EXPANDER_PORT_COUNT == USBC_PORT_COUNT);
-
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80us
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 6 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 1500,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = SECOND,
-	.actual_key_mask = {
-		0x3c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-const struct pwm_t pwm_channels[] = {
-	[PWM_CH_FAN] = {
-		.channel = 0,
-		.flags = PWM_CONFIG_OPEN_DRAIN,
-		.freq = 25000,
-	},
-	[PWM_CH_KBLIGHT] = {
-		.channel = 1,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-	[PWM_CH_LED_CHRG] = {
-		.channel = 2,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-	[PWM_CH_LED_FULL] = {
-		.channel = 3,
-		.flags = PWM_CONFIG_DSLEEP,
-		.freq = 100,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
-
-const struct mft_t mft_channels[] = {
-	[MFT_CH_0] = {
-		.module = NPCX_MFT_MODULE_1,
-		.clk_src = TCKC_LFCLK,
-		.pwm_id = PWM_CH_FAN,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
-
-const struct fan_conf fan_conf_0 = {
-	.flags = FAN_USE_RPM_MODE,
-	.ch = MFT_CH_0,	/* Use MFT id to control fan */
-	.pgood_gpio = GPIO_S0_PGOOD,
-	.enable_gpio = -1,
-};
-const struct fan_rpm fan_rpm_0 = {
-	.rpm_min = 1000,
-	.rpm_start = 1000,
-	.rpm_max = 6500,
-};
-const struct fan_t fans[] = {
-	[FAN_CH_0] = {
-		.conf = &fan_conf_0,
-		.rpm = &fan_rpm_0,
-	},
-};
-BUILD_ASSERT(ARRAY_SIZE(fans) == FAN_CH_COUNT);
-
-/*
- * USB C0 port SBU mux use standalone FSUSB42UMX
- * chip and it needs a board specific driver.
- * Overall, it will use chained mux framework.
- */
-static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state,
-			      bool *ack_required)
-{
-	/* This driver does not use host command ACKs */
-	*ack_required = false;
-
-	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
-	else
-		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0);
-
-	return EC_SUCCESS;
-}
-
-static void setup_mux(void)
-{
-	switch (board_get_usb_c1_mux()) {
-	case USB_C1_MUX_PS8818:
-		CPRINTSUSB("C1: Setting PS8818 mux");
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_ps8818;
-		break;
-	case USB_C1_MUX_ANX7451:
-		CPRINTSUSB("C1: Setting ANX7451 mux");
-		usb_muxes[USBC_PORT_C1].next_mux = &usbc1_anx7451;
-		break;
-	default:
-		CPRINTSUSB("C1: Mux is unknown");
-	}
-}
-DECLARE_HOOK(HOOK_INIT, setup_mux, HOOK_PRIO_INIT_I2C);
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 &&
-			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-	int cur_port = charge_manager_get_active_charge_port();
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * If this port had booted in dead battery mode, go
-			 * ahead and reset it so EN_SNK responds properly.
-			 */
-			if (nct38xx_get_boot_type(i) ==
-						NCT38XX_BOOT_DEAD_BATTERY) {
-				reset_nct38xx_port(cur_port);
-				pd_set_error_recovery(i);
-			}
-
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	} else if (!is_valid_port) {
-		return EC_ERROR_INVAL;
-	}
-
-
-	/* Check if the port is sourcing VBUS. */
-	if (tcpm_get_src_ctrl(port)) {
-		CPRINTSUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Disallow changing ports if we booted in dead battery mode and don't
-	 * have sufficient power to withstand Vbus loss.  The NCT3807 may
-	 * continue to keep EN_SNK low on the original port and allow a
-	 * dangerous level of voltage to pass through to the initial charge
-	 * port (see b/183660105)
-	 *
-	 * If we do have sufficient power, then reset the dead battery port and
-	 * set up Type-C error recovery on its connection.
-	 */
-	if (cur_port != CHARGE_PORT_NONE &&
-			port != cur_port &&
-			nct38xx_get_boot_type(cur_port) ==
-						NCT38XX_BOOT_DEAD_BATTERY) {
-		if (pd_is_battery_capable()) {
-			reset_nct38xx_port(cur_port);
-			pd_set_error_recovery(cur_port);
-		} else {
-			CPRINTSUSB("Battery too low for charge port change");
-			return EC_ERROR_INVAL;
-		}
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-int board_is_i2c_port_powered(int port)
-{
-	switch (port) {
-	case I2C_PORT_USB_MUX:
-	case I2C_PORT_SENSOR:
-		/* USB mux and sensor i2c bus is unpowered in Z1 */
-		return chipset_in_state(CHIPSET_STATE_HARD_OFF) ? 0 : 1;
-	case I2C_PORT_THERMAL_AP:
-		/* SOC thermal i2c bus is unpowered in S0i3/S3/S5/Z1 */
-		return chipset_in_state(CHIPSET_STATE_ANY_OFF |
-					CHIPSET_STATE_ANY_SUSPEND) ? 0 : 1;
-	default:
-		return 1;
-	}
-}
-
-/*
- * In the AOZ1380 PPC, there are no programmable features.  We use
- * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
- * current limits.
- */
-int board_aoz1380_set_vbus_source_current_limit(int port,
-						enum tcpc_rp_value rp)
-{
-	int rv;
-
-	/* Use the TCPC to set the current limit */
-	rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN,
-			    (rp == TYPEC_RP_3A0) ? 1 : 0);
-
-	return rv;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
-
-void sbu_fault_interrupt(enum ioex_signal signal)
-{
-	int port = (signal == IOEX_USB_C0_SBU_FAULT_ODL) ? 0 : 1;
-
-	pd_handle_overcurrent(port);
-}
-
-static void set_ac_prochot(void)
-{
-	isl9241_set_ac_prochot(CHARGER_SOLO, GUYBRUSH_AC_PROCHOT_CURRENT_MA);
-}
-DECLARE_HOOK(HOOK_INIT, set_ac_prochot, HOOK_PRIO_DEFAULT);
-
-void tcpc_alert_event(enum gpio_signal signal)
-{
-	int port;
-
-	switch (signal) {
-	case GPIO_USB_C0_TCPC_INT_ODL:
-		port = 0;
-		break;
-	case GPIO_USB_C1_TCPC_INT_ODL:
-		port = 1;
-		break;
-	default:
-		return;
-	}
-
-	schedule_deferred_pd_interrupt(port);
-}
-
-static void reset_nct38xx_port(int port)
-{
-	enum gpio_signal reset_gpio_l;
-
-	if (port == USBC_PORT_C0)
-		reset_gpio_l = GPIO_USB_C0_TCPC_RST_L;
-	else if (port == USBC_PORT_C1)
-		reset_gpio_l = GPIO_USB_C1_TCPC_RST_L;
-	else
-		/* Invalid port: do nothing */
-		return;
-
-	gpio_set_level(reset_gpio_l, 0);
-	msleep(NCT38XX_RESET_HOLD_DELAY_MS);
-	gpio_set_level(reset_gpio_l, 1);
-	nct38xx_reset_notify(port);
-	if (NCT3807_RESET_POST_DELAY_MS != 0)
-		msleep(NCT3807_RESET_POST_DELAY_MS);
-}
-
-
-void board_reset_pd_mcu(void)
-{
-	/* Reset TCPC0 */
-	reset_nct38xx_port(USBC_PORT_C0);
-
-	/* Reset TCPC1 */
-	reset_nct38xx_port(USBC_PORT_C1);
-}
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-
-	/*
-	 * Check which port has the ALERT line set and ignore if that TCPC has
-	 * its reset line active.
-	 */
-	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C0_TCPC_RST_L) != 0)
-			status |= PD_STATUS_TCPC_ALERT_0;
-	}
-
-	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL)) {
-		if (gpio_get_level(GPIO_USB_C1_TCPC_RST_L) != 0)
-			status |= PD_STATUS_TCPC_ALERT_1;
-	}
-
-	return status;
-}
-
-void ppc_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_PPC_INT_ODL:
-		aoz1380_interrupt(USBC_PORT_C0);
-		break;
-
-	case GPIO_USB_C1_PPC_INT_ODL:
-		nx20p348x_interrupt(USBC_PORT_C1);
-		break;
-
-	default:
-		break;
-	}
-}
-
-void bc12_interrupt(enum gpio_signal signal)
-{
-	switch (signal) {
-	case GPIO_USB_C0_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
-		break;
-
-	case GPIO_USB_C1_BC12_INT_ODL:
-		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
-		break;
-
-	default:
-		break;
-	}
-}
-
-/**
- * Return if VBUS is sagging too low
- */
-int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
-{
-	int voltage = 0;
-	int rv;
-
-	rv = charger_get_vbus_voltage(port, &voltage);
-
-	if (rv) {
-		CPRINTSUSB("%s rv=%d", __func__, rv);
-		return 0;
-	}
-
-	/*
-	 * b/168569046: The ISL9241 sometimes incorrectly reports 0 for unknown
-	 * reason, causing ramp to stop at 0.5A. Workaround this by ignoring 0.
-	 * This partly defeats the point of ramping, but will still catch
-	 * VBUS below 4.5V and above 0V.
-	 */
-	if (voltage == 0) {
-		CPRINTSUSB("%s vbus=0", __func__);
-		return 0;
-	}
-
-	if (voltage < BC12_MIN_VOLTAGE)
-		CPRINTSUSB("%s vbus=%d", __func__, voltage);
-
-	return voltage < BC12_MIN_VOLTAGE;
-}
-
-/**
- * b/175324615: On G3->S5, wait for RSMRST_L to be deasserted before asserting
- * PCH_PWRBTN_L.
- */
-void board_pwrbtn_to_pch(int level)
-{
-	timestamp_t start;
-	const uint32_t timeout_rsmrst_rise_us = 30 * MSEC;
-
-	/* Add delay for G3 exit if asserting PWRBTN_L and RSMRST_L is low. */
-	if (!level && !gpio_get_level(GPIO_PCH_RSMRST_L)) {
-		start = get_time();
-		do {
-			usleep(200);
-			if (gpio_get_level(GPIO_PCH_RSMRST_L))
-				break;
-		} while (time_since32(start) < timeout_rsmrst_rise_us);
-
-		if (!gpio_get_level(GPIO_PCH_RSMRST_L))
-			ccprints("Error pwrbtn: RSMRST_L still low");
-
-		msleep(G3_TO_PWRBTN_DELAY_MS);
-	}
-	gpio_set_level(GPIO_PCH_PWRBTN_L, level);
-}
-
-void board_hibernate(void)
-{
-	int port;
-
-	/*
-	 * If we are charging, then drop the Vbus level down to 5V to ensure
-	 * that we don't get locked out of the 6.8V OVLO for our PPCs in
-	 * dead-battery mode. This is needed when the TCPC/PPC rails go away.
-	 * (b/79218851, b/143778351, b/147007265)
-	 */
-	port = charge_manager_get_active_charge_port();
-	if (port != CHARGE_PORT_NONE) {
-		pd_request_source_voltage(port, SAFE_RESET_VBUS_MV);
-
-		/* Give PD task and PPC chip time to get to 5V */
-		msleep(SAFE_RESET_VBUS_DELAY_MS);
-	}
-
-	/* Try to put our battery fuel gauge into sleep mode */
-	if (battery_sleep_fuel_gauge() != EC_SUCCESS)
-		cprints(CC_SYSTEM, "Failed to send battery sleep command");
-}
-
-__overridable enum ec_error_list
-board_a1_ps8811_retimer_init(const struct usb_mux *me)
-{
-	return EC_SUCCESS;
-}
-
-static int baseboard_a1_ps8811_retimer_init(const struct usb_mux *me)
-{
-	int rv;
-	int tries = 2;
-
-	do {
-		int val;
-
-		rv = ps8811_i2c_read(me, PS8811_REG_PAGE1,
-				     PS8811_REG1_USB_BEQ_LEVEL, &val);
-	} while (rv && --tries);
-
-	if (rv) {
-		CPRINTSUSB("A1: PS8811 retimer not detected!");
-		return rv;
-	}
-	CPRINTSUSB("A1: PS8811 retimer detected");
-	rv = board_a1_ps8811_retimer_init(me);
-	if (rv)
-		CPRINTSUSB("A1: Error during PS8811 setup rv:%d", rv);
-	return rv;
-}
-
-/* PS8811 is just a type-A USB retimer, reusing mux structure for convience. */
-const struct usb_mux usba1_ps8811 = {
-	.usb_port = USBA_PORT_A1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.i2c_addr_flags = PS8811_I2C_ADDR_FLAGS3,
-	.board_init = &baseboard_a1_ps8811_retimer_init,
-};
-
-__overridable enum ec_error_list
-board_a1_anx7491_retimer_init(const struct usb_mux *me)
-{
-	return EC_SUCCESS;
-}
-
-static int baseboard_a1_anx7491_retimer_init(const struct usb_mux *me)
-{
-	int rv;
-	int tries = 2;
-
-	do {
-		int val;
-
-		rv = i2c_read8(me->i2c_port, me->i2c_addr_flags, 0, &val);
-	} while (rv && --tries);
-	if (rv) {
-		CPRINTSUSB("A1: ANX7491 retimer not detected!");
-		return rv;
-	}
-	CPRINTSUSB("A1: ANX7491 retimer detected");
-	rv = board_a1_anx7491_retimer_init(me);
-	if (rv)
-		CPRINTSUSB("A1: Error during ANX7491 setup rv:%d", rv);
-	return rv;
-}
-
-/* ANX7491 is just a type-A USB retimer, reusing mux structure for convience. */
-const struct usb_mux usba1_anx7491 = {
-	.usb_port = USBA_PORT_A1,
-	.i2c_port = I2C_PORT_TCPC1,
-	.i2c_addr_flags = ANX7491_I2C_ADDR0_FLAGS,
-	.board_init = &baseboard_a1_anx7491_retimer_init,
-};
-
-void baseboard_a1_retimer_setup(void)
-{
-	struct usb_mux a1_retimer;
-	switch (board_get_usb_a1_retimer()) {
-	case USB_A1_RETIMER_ANX7491:
-		a1_retimer = usba1_anx7491;
-		break;
-	case USB_A1_RETIMER_PS8811:
-		a1_retimer = usba1_ps8811;
-		break;
-	default:
-		CPRINTSUSB("A1: Unknown retimer!");
-		return;
-	}
-	a1_retimer.board_init(&a1_retimer);
-}
-DECLARE_DEFERRED(baseboard_a1_retimer_setup);
-
-static void baseboard_chipset_suspend(void)
-{
-	/* Disable display and keyboard backlights. */
-	gpio_set_level(GPIO_EC_DISABLE_DISP_BL, 1);
-	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend,
-	     HOOK_PRIO_DEFAULT);
-
-static void baseboard_chipset_resume(void)
-{
-	/* Enable display and keyboard backlights. */
-	gpio_set_level(GPIO_EC_DISABLE_DISP_BL, 0);
-	ioex_set_level(IOEX_USB_A1_RETIMER_EN, 1);
-	/* Some retimers take several ms to be ready, so defer setup call */
-	hook_call_deferred(&baseboard_a1_retimer_setup_data, 20 * MSEC);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT);
-
-void board_overcurrent_event(int port, int is_overcurrented)
-{
-	switch (port) {
-	case USBC_PORT_C0:
-	case USBC_PORT_C1:
-		gpio_set_level(GPIO_USB_C0_C1_FAULT_ODL, !is_overcurrented);
-		break;
-
-	default:
-		break;
-	}
-}
-
-void baseboard_en_pwr_pcore_s0(enum gpio_signal signal)
-{
-
-	/* EC must AND signals PG_LPDDR4X_S3_OD and PG_GROUPC_S0_OD */
-	gpio_set_level(GPIO_EN_PWR_PCORE_S0_R,
-					gpio_get_level(GPIO_PG_LPDDR4X_S3_OD) &&
-					gpio_get_level(GPIO_PG_GROUPC_S0_OD));
-}
-
-void baseboard_en_pwr_s0(enum gpio_signal signal)
-{
-
-	/* EC must AND signals SLP_S3_L and PG_PWR_S5 */
-	gpio_set_level(GPIO_EN_PWR_S0_R,
-					gpio_get_level(GPIO_SLP_S3_L) &&
-					gpio_get_level(GPIO_PG_PWR_S5));
-
-	/* Now chain off to the normal power signal interrupt handler. */
-	power_signal_interrupt(signal);
-}
diff --git a/baseboard/guybrush/baseboard.h b/baseboard/guybrush/baseboard.h
deleted file mode 100644
index ef1338c5d5..0000000000
--- a/baseboard/guybrush/baseboard.h
+++ /dev/null
@@ -1,373 +0,0 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Guybrush baseboard configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/* NPCX9 config */
-#define CONFIG_PORT80_4_BYTE
-#define NPCX9_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
-
-/* Optional features */
-#define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
-#define CONFIG_LTO /* Link-Time Optimizations to reduce code size */
-#define CONFIG_I2C_DEBUG /* Print i2c traces */
-#define CONFIG_CMD_S5_TIMEOUT /* Allow a user-specified timeout to exit S5 */
-
-#undef CONFIG_UART_TX_BUF_SIZE
-#define CONFIG_UART_TX_BUF_SIZE 4096
-
-/* Vboot Config */
-#define CONFIG_CRC8
-#define CONFIG_VBOOT_EFS2
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_PACKET_MODE_EN	GPIO_EC_GSC_PACKET_MODE
-
-/* CBI Config */
-#define CONFIG_CBI_EEPROM
-#define CONFIG_BOARD_VERSION_CBI
-
-/* Power Config */
-#define CONFIG_CHIPSET_X86_RSMRST_DELAY
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
-#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_HIBERNATE_PSL
-#define CONFIG_LOW_POWER_IDLE
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_TO_PCH_CUSTOM
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_COMMON
-#define CONFIG_POWER_S0IX
-#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
-#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
-#define G3_TO_PWRBTN_DELAY_MS 16
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_EN_PWR_A		GPIO_EN_PWR_S5
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_SOC_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L	GPIO_EC_SOC_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S3_S0I3_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L	GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_SOC_PWR_GOOD
-#define GPIO_PCH_WAKE_L		GPIO_EC_SOC_WAKE_L
-#define GPIO_POWER_BUTTON_L	GPIO_MECH_PWR_BTN_ODL
-#define GPIO_S0_PGOOD		GPIO_PG_PCORE_S0_R_OD
-#define GPIO_S5_PGOOD		GPIO_PG_PWR_S5
-#define GPIO_SYS_RESET_L	GPIO_EC_SYS_RST_L
-#define SAFE_RESET_VBUS_DELAY_MS 900
-#define SAFE_RESET_VBUS_MV 5000
-/*
- * On power-on, H1 releases the EC from reset but then quickly asserts and
- * releases the reset a second time. This means the EC sees 2 resets:
- * (1) power-on reset, (2) reset-pin reset. This config will
- * allow the second reset to be treated as a power-on.
- */
-#define CONFIG_BOARD_RESET_AFTER_POWER_ON
-
-/* Thermal Config */
-#define CONFIG_ADC
-#define CONFIG_AMD_SB_RMI
-#define CONFIG_AMD_STT
-#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
-#define CONFIG_THROTTLE_AP
-#define CONFIG_TEMP_SENSOR_SB_TSI
-#define CONFIG_TEMP_SENSOR_TMP112
-#define CONFIG_THERMISTOR
-#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-#define GPIO_CPU_PROCHOT	GPIO_PROCHOT_ODL
-
-/* Flash Config */
-/* See config_chip-npcx9.h for SPI flash configuration */
-#undef CONFIG_SPI_FLASH /* Don't enable external flash interface */
-#define GPIO_WP_L			GPIO_EC_WP_L
-
-/* Host communication */
-#define CONFIG_CMD_CHARGEN
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
-#define GPIO_EC_INT_L		GPIO_EC_SOC_INT_L
-
-/* Chipset config */
-#define CONFIG_CHIPSET_CEZANNE
-#define CONFIG_CHIPSET_CAN_THROTTLE
-#define CONFIG_CHIPSET_RESET_HOOK
-
-/* Keyboard Config */
-#define CONFIG_KEYBOARD_BACKLIGHT
-
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_VIVALDI
-#define GPIO_EN_KEYBOARD_BACKLIGHT	GPIO_EN_KB_BL
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
-
-/* Sensors */
-#ifdef HAS_TASK_MOTIONSENSE
-
-#define CONFIG_TABLET_MODE
-#define CONFIG_GMR_TABLET_MODE
-#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE
-#define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
-#define CONFIG_LID_ANGLE
-#define CONFIG_LID_ANGLE_UPDATE
-#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
-#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
-
-/* Enable sensor fifo, must also define the _SIZE and _THRES */
-#define CONFIG_ACCEL_FIFO
-/* FIFO size is a power of 2. */
-#define CONFIG_ACCEL_FIFO_SIZE 256
-/* Depends on how fast the AP boots and typical ODRs. */
-#define CONFIG_ACCEL_FIFO_THRES (CONFIG_ACCEL_FIFO_SIZE / 3)
-
-/* Sensors without hardware FIFO are in forced mode */
-#define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL)
-#endif  /* HAS_TASK_MOTIONSENSE */
-
-/* Backlight config */
-#define CONFIG_BACKLIGHT_LID
-#define CONFIG_BACKLIGHT_LID_ACTIVE_LOW
-#define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_DISABLE_DISP_BL
-
-/* Battery Config */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_SMART
-#define CONFIG_BATTERY_V2
-#define CONFIG_BATTERY_COUNT 1
-#define CONFIG_HOSTCMD_BATTERY_V2
-#define CONFIG_BC12_DETECT_PI3USB9201
-
-/* Charger Config */
-#define CONFIG_CHARGER
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512
-#define CONFIG_CHARGER_ISL9241
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
-
-/*
- * EC will boot AP to depthcharge if: (BAT >= 2%) || (AC >= 50W)
- * CONFIG_CHARGER_LIMIT_* is not set, so there is no additional restriction on
- * Depthcharge to boot OS.
- */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		50000
-
-/*
- * We would prefer to use CONFIG_CHARGE_RAMP_HW to enable legacy BC1.2 charging
- * but that feature of ISL9241 is broken (b/160287056) so we have to use
- * CONFIG_CHARGE_RAMP_SW instead.
- */
-#define CONFIG_CHARGE_RAMP_SW
-
-/* USB Type C and USB PD config */
-#define CONFIG_USB_PD_REV30
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_DRP_ACC_TRYSRC
-/* TODO: Enable TCPMv2 Fast Role Swap (FRS) */
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_CMD_TCPC_DUMP
-#define CONFIG_USB_CHARGER
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_5V_EN_CUSTOM
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DISCHARGE_TCPC
-#define CONFIG_USB_PD_DP_HPD_GPIO
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_TCPC_LOW_POWER
-#define CONFIG_USB_PD_TCPM_MUX
-#define CONFIG_USB_PD_TCPM_NCT38XX
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_PD_VBUS_DETECT_TCPC
-#define CONFIG_USBC_PPC
-#define CONFIG_USBC_PPC_SBU
-#define CONFIG_USBC_PPC_AOZ1380
-#define CONFIG_USBC_RETIMER_PI3HDX1204
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_SS_MUX_DFP_ONLY
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-#define CONFIG_USB_PD_PORT_MAX_COUNT 2
-#define CONFIG_USBC_PPC_NX20P3483
-#define CONFIG_USBC_RETIMER_PS8811
-#define CONFIG_USBC_RETIMER_PS8818
-#define CONFIG_USB_MUX_RUNTIME_CONFIG
-#define CONFIG_USB_MUX_AMD_FP6
-
-#define GPIO_USB_C0_DP_HPD GPIO_USB_C0_HPD
-#define GPIO_USB_C1_DP_HPD GPIO_USB_C1_HPD
-
-#define CONFIG_IO_EXPANDER
-#define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT
-
-/* TODO(b/176988382): Tune values for guybrush */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
-
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_CURRENT_MA	5000
-#define PD_MAX_VOLTAGE_MV	20000
-/* Max Power = 100 W */
-#define PD_MAX_POWER_MW		((PD_MAX_VOLTAGE_MV * PD_MAX_CURRENT_MA) / 1000)
-
-/* USB-A config */
-#define USB_PORT_COUNT USBA_PORT_COUNT
-#define CONFIG_USB_PORT_POWER_SMART
-#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
-#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
-#define CONFIG_USB_PORT_POWER_SMART_INVERTED
-
-#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_LIMIT_SDP
-#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_LIMIT_SDP_DB
-
-/* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */
-#define GUYBRUSH_AC_PROCHOT_CURRENT_MA 3328
-
-/*
- * USB ID - This is allocated specifically for Guybrush
- */
-#define CONFIG_USB_PID 0x504D
-
-/* BC 1.2 */
-/*
- * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input current
- * until voltage drops to 4.5V. Don't go lower than this to be kind to the
- * charger (see b/67964166).
- */
-#define BC12_MIN_VOLTAGE 4500
-
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
-#define CONFIG_I2C_CONTROLLER
-#define CONFIG_I2C_UPDATE_IF_CHANGED
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT1_0
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT4_1
-#define I2C_PORT_CHARGER	I2C_PORT_POWER
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT6_1
-#define I2C_PORT_THERMAL_AP	NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-/* Volume Button Config */
-#define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
-
-/* Fan Config */
-#define CONFIG_FANS FAN_CH_COUNT
-/* TODO: Set CONFIG_FAN_INIT_SPEED, defaults to 100 */
-
-/* LED Config */
-#define CONFIG_PWM
-#define CONFIG_PWM_KBLIGHT
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-#include "registers.h"
-
-/* Power input signals */
-enum power_signal {
-	X86_SLP_S0_N,		/* SOC  -> SLP_S3_S0I3_L */
-	X86_SLP_S3_N,		/* SOC  -> SLP_S3_L */
-	X86_SLP_S5_N,		/* SOC  -> SLP_S5_L */
-
-	X86_S0_PGOOD,		/* PMIC -> S0_PWROK_OD */
-	X86_S5_PGOOD,		/* PMIC -> S5_PWROK */
-
-	/* Number of X86 signals */
-	POWER_SIGNAL_COUNT,
-};
-
-/* USB-C ports */
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
-
-/* USB-A ports */
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
-
-/* TMP112 sensors */
-enum tmp112_sensor {
-	TMP112_SOC,
-	TMP112_AMB,
-	TMP112_COUNT,
-};
-
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
-
-/* PWM Channels */
-enum pwm_channel {
-	PWM_CH_FAN = 0,
-	PWM_CH_KBLIGHT,
-	PWM_CH_LED_CHRG,
-	PWM_CH_LED_FULL,
-	PWM_CH_COUNT
-};
-
-/* Fan Channels */
-enum fan_channel {
-	FAN_CH_0 = 0,
-	/* Number of FAN channels */
-	FAN_CH_COUNT,
-};
-enum mft_channel {
-	MFT_CH_0 = 0,
-	/* Number of MFT channels */
-	MFT_CH_COUNT,
-};
-
-/* Common definition for the USB PD interrupt handlers. */
-void tcpc_alert_event(enum gpio_signal signal);
-void bc12_interrupt(enum gpio_signal signal);
-void ppc_interrupt(enum gpio_signal signal);
-void sbu_fault_interrupt(enum ioex_signal signal);
-
-void baseboard_en_pwr_pcore_s0(enum gpio_signal signal);
-void baseboard_en_pwr_s0(enum gpio_signal signal);
-
-int board_get_soc_temp_k(int idx, int *temp_k);
-
-/* CBI utility functions */
-uint32_t get_sku_id(void);
-uint32_t get_board_version(void);
-uint32_t get_fw_config(void);
-/* Board callback after CBI has been initialized */
-__overridable void board_cbi_init(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/guybrush/build.mk b/baseboard/guybrush/build.mk
deleted file mode 100644
index 976ff2c931..0000000000
--- a/baseboard/guybrush/build.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# -*- makefile -*-
-# Copyright 2020 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Guybrush baseboard specific files build
-#
-
-CHIP:=npcx
-CHIP_FAMILY:=npcx9
-CHIP_VARIANT:=npcx9m3f
-
-baseboard-y=baseboard.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
-baseboard-$(CONFIG_CBI_EEPROM)+=cbi.o
\ No newline at end of file
diff --git a/baseboard/guybrush/cbi.c b/baseboard/guybrush/cbi.c
deleted file mode 100644
index 6d66b826dc..0000000000
--- a/baseboard/guybrush/cbi.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Guybrush CrOS Board Info(CBI) utilities */
-
-#include "base_fw_config.h"
-#include "console.h"
-#include "common.h"
-#include "cros_board_info.h"
-#include "hooks.h"
-
-uint32_t get_sku_id(void)
-{
-	static uint32_t sku_id;
-
-	if (sku_id == 0) {
-		uint32_t val;
-
-		if (cbi_get_sku_id(&val) != EC_SUCCESS)
-			return 0;
-		sku_id = val;
-	}
-	return sku_id;
-}
-
-uint32_t get_board_version(void)
-{
-	static uint32_t board_version;
-
-	if (board_version == 0) {
-		uint32_t val;
-
-		if (cbi_get_board_version(&val) != EC_SUCCESS)
-			return -1;
-		board_version = val;
-	}
-	return board_version;
-}
-
-uint32_t get_fw_config(void)
-{
-	static uint32_t fw_config = UNINITIALIZED_FW_CONFIG;
-
-	if (fw_config == UNINITIALIZED_FW_CONFIG) {
-		uint32_t val;
-
-		if (cbi_get_fw_config(&val) != EC_SUCCESS)
-			return UNINITIALIZED_FW_CONFIG;
-		fw_config = val;
-	}
-	return  fw_config;
-}
-
-
-int get_fw_config_field(uint8_t offset, uint8_t width)
-{
-	uint32_t fw_config = get_fw_config();
-
-	if (fw_config == UNINITIALIZED_FW_CONFIG)
-		return -1;
-
-	return (fw_config >> offset) & ((1 << width) - 1);
-}
-
-
-__overridable void board_cbi_init(void)
-{
-}
-
-static void cbi_init(void)
-{
-	uint32_t board_ver = get_board_version();
-	uint32_t sku_id = get_sku_id();
-	uint32_t fw_config = get_fw_config();
-
-	if (board_ver != 0)
-		ccprints("Board Version: %d (0x%x)", board_ver, board_ver);
-	else
-		ccprints("Board Version: not set in cbi");
-
-	if (sku_id != 0)
-		ccprints("SKU ID: %d (0x%x)", sku_id, sku_id);
-	else
-		ccprints("SKU ID: not set in cbi");
-
-	if (fw_config != UNINITIALIZED_FW_CONFIG)
-		ccprints("FW Config: %d (0x%x)", fw_config, fw_config);
-	else
-		ccprints("FW Config: not set in cbi");
-
-	/* Allow the board project to make runtime changes based on CBI data */
-	board_cbi_init();
-}
-DECLARE_HOOK(HOOK_INIT, cbi_init, HOOK_PRIO_INIT_I2C + 1);
diff --git a/baseboard/guybrush/usb_pd_policy.c b/baseboard/guybrush/usb_pd_policy.c
deleted file mode 100644
index 79725e827a..0000000000
--- a/baseboard/guybrush/usb_pd_policy.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright 2021 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Shared USB-C policy for Zork boards */
-
-#include "charge_manager.h"
-#include "chipset.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "ioexpander.h"
-#include "system.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-int pd_check_vconn_swap(int port)
-{
-	/*
-	 * Do not allow vconn swap 5V rail is off
-	 * S5_PGOOD depends on PG_PP5000_S5 being asserted,
-	 * so GPIO_S5_PGOOD is a reasonable proxy for PP5000_S5
-	 */
-	return gpio_get_level(GPIO_S5_PGOOD);
-}
-
-void pd_power_supply_reset(int port)
-{
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
-		pd_set_vbus_discharge(port, 1);
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
-		pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-__override int board_pd_set_frs_enable(int port, int enable)
-{
-	/*
-	 * Both PPCs require the FRS GPIO to be set as soon as FRS capability
-	 * is established.
-	 */
-	if (port == 0)
-		ioex_set_level(IOEX_USB_C0_TCPC_FASTSW_CTL_EN, enable);
-	else if (port == 1)
-		ioex_set_level(IOEX_USB_C1_TCPC_FASTSW_CTL_EN, enable);
-
-	return EC_SUCCESS;
-}
-
-/* Used by Vbus discharge common code with CONFIG_USB_PD_DISCHARGE */
-int board_vbus_source_enabled(int port)
-{
-	return tcpm_get_src_ctrl(port);
-}
-
-/* Used by USB charger task with CONFIG_USB_PD_5V_EN_CUSTOM */
-int board_is_sourcing_vbus(int port)
-{
-	return board_vbus_source_enabled(port);
-}