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| author | Rob Barnes <robbarnes@google.com> | 2021-01-08 11:17:13 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-01-19 05:51:25 +0000 |
| commit | 510297b805e9d76c99b72ac6e25053b153cab38d (patch) | |
| tree | 5378974945b05af666d3f6d161d12429e0e497b8 /baseboard/guybrush | |
| parent | 34ffd662489fedae22be6a5428221a9a827ab937 (diff) | |
| download | chrome-ec-510297b805e9d76c99b72ac6e25053b153cab38d.tar.gz | |
guybrush: AND signals SLP_S3_L and PG_PWR_S5
Discrete AND gate was replaced with EC logic.
AND signals SLP_S3_L and PG_PWR_S5 to drive EN_PWR_S0.
BUG=b:177071412
TEST=Build
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I473a82dfe8e04f06cc8d2fc0639c9aaed401069a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2618387
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Diffstat (limited to 'baseboard/guybrush')
| -rw-r--r-- | baseboard/guybrush/base_gpio.inc | 4 | ||||
| -rw-r--r-- | baseboard/guybrush/baseboard.c | 11 | ||||
| -rw-r--r-- | baseboard/guybrush/baseboard.h | 1 |
3 files changed, 14 insertions, 2 deletions
diff --git a/baseboard/guybrush/base_gpio.inc b/baseboard/guybrush/base_gpio.inc index 17ba1e1a31..16c3e6e97c 100644 --- a/baseboard/guybrush/base_gpio.inc +++ b/baseboard/guybrush/base_gpio.inc @@ -14,10 +14,10 @@ ALTERNATE( PIN_MASK(6, BIT(4) | BIT(5)), 0, MODULE_UART, 0) /* UART_EC_TX_GS /* Power Signals */ GPIO_INT(MECH_PWR_BTN_ODL, PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, power_button_interrupt) /* Mechanical Power Button */ GPIO_INT(EC_PWR_BTN_ODL, PIN(0, 1), GPIO_INT_BOTH, power_button_interrupt) /* Power Button */ -GPIO_INT(SLP_S3_L, PIN(6, 1), GPIO_INT_BOTH, power_signal_interrupt) /* Sleep S3 */ +GPIO_INT(SLP_S3_L, PIN(6, 1), GPIO_INT_BOTH, baseboard_en_pwr_s0) /* Sleep S3 */ GPIO_INT(SLP_S5_L, PIN(7, 2), GPIO_INT_BOTH, power_signal_interrupt) /* Sleep S5 */ GPIO_INT(SLP_S3_S0I3_L, PIN(7, 4), GPIO_INT_BOTH, power_signal_interrupt) /* Sleep S0ix */ -GPIO_INT(PG_PWR_S5, PIN(C, 0), GPIO_INT_BOTH, power_signal_interrupt) /* S5 Power OK */ +GPIO_INT(PG_PWR_S5, PIN(C, 0), GPIO_INT_BOTH, baseboard_en_pwr_s0) /* S5 Power OK */ GPIO_INT(PG_PCORE_S0_R_OD, PIN(B, 6), GPIO_INT_BOTH, power_signal_interrupt) /* S0 Power OK */ GPIO_INT(ACOK_OD, PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt) /* AC Power Present */ GPIO_INT(EC_PCORE_INT_ODL, PIN(F, 0), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt) /* Power Core Interrupt */ diff --git a/baseboard/guybrush/baseboard.c b/baseboard/guybrush/baseboard.c index 429d751f32..42804dbe68 100644 --- a/baseboard/guybrush/baseboard.c +++ b/baseboard/guybrush/baseboard.c @@ -719,3 +719,14 @@ void baseboard_en_pwr_pcore_s0(enum gpio_signal signal) gpio_get_level(GPIO_PG_GROUPC_S0_OD)); } +void baseboard_en_pwr_s0(enum gpio_signal signal) +{ + + /* EC must AND signals SLP_S3_L and PG_PWR_S5 */ + gpio_set_level(GPIO_EN_PWR_S0_R, + gpio_get_level(GPIO_SLP_S3_L) && + gpio_get_level(GPIO_PG_PWR_S5)); + + /* Now chain off to the normal power signal interrupt handler. */ + power_signal_interrupt(signal); +} diff --git a/baseboard/guybrush/baseboard.h b/baseboard/guybrush/baseboard.h index 1c686da351..abf3f412ef 100644 --- a/baseboard/guybrush/baseboard.h +++ b/baseboard/guybrush/baseboard.h @@ -274,6 +274,7 @@ void sbu_fault_interrupt(enum ioex_signal signal); int baseboard_get_temp(int idx, int *temp_ptr); void baseboard_en_pwr_pcore_s0(enum gpio_signal signal); +void baseboard_en_pwr_s0(enum gpio_signal signal); #endif /* !__ASSEMBLER__ */ |