honeybuns: Enable USB-EP support

This CL adds configs/structs required for USB-EP support for both
quiche and gingerbread. This CL also adds usbc support code to RO so
that Rd is being presented on both CC lines in RO.

In addition, there is some clean up for I2C port names and the debug
gpio utility function.

BUG=b:172493899
BRANCH=None
TEST=tested on quiche and verified that the USB-EP was enumerated
RST EP0 3220
RST EP0 3220
RST EP0 3220
RST EP0 3220
SETAD ae
[8.069004 Jumping to image RW]

Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I8d65ba55eecc2b82047a8cd433611f639af0c5ed
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2699453
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Sam Hurst <shurst@google.com>
Commit-Queue: Scott Collyer <scollyer@chromium.org>

4 files changed, 180 insertions, 7 deletions

diff --git a/baseboard/honeybuns/baseboard.c b/baseboard/honeybuns/baseboard.c
index e702496cad..62a576be02 100644
--- a/baseboard/honeybuns/baseboard.c
+++ b/baseboard/honeybuns/baseboard.c
@@ -29,9 +29,8 @@ static void board_power_sequence(void)
 /******************************************************************************/
 /* I2C port map configuration */
 const struct i2c_port_t i2c_ports[] = {
-	{"usbc",   I2C_PORT_USBC,   400, GPIO_EC_I2C1_SCL, GPIO_EC_I2C1_SDA},
-	{"usb_mst",  I2C_PORT_MST,  400, GPIO_EC_I2C2_SCL, GPIO_EC_I2C2_SDA},
-	{"eeprom",  I2C_PORT_EEPROM,  400, GPIO_EC_I2C3_SCL, GPIO_EC_I2C3_SDA},
+	{"i2c1",  I2C_PORT_I2C1,  400, GPIO_EC_I2C1_SCL, GPIO_EC_I2C1_SDA},
+	{"i2c3",  I2C_PORT_I2C3,  400, GPIO_EC_I2C3_SCL, GPIO_EC_I2C3_SDA},
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
 
@@ -40,5 +39,13 @@ static void baseboard_init(void)
 	/* Turn on power rails */
 	board_power_sequence();
 	CPRINTS("board: Power rails enabled");
+
+#ifdef SECTION_IS_RW
+
+#else
+	/* Set up host port usbc to present Rd on CC lines */
+	if(baseboard_usbc_init(USB_PD_PORT_HOST))
+		CPRINTS("usbc: Failed to set up sink path");
+#endif
 }
 DECLARE_HOOK(HOOK_INIT, baseboard_init, HOOK_PRIO_DEFAULT);
diff --git a/baseboard/honeybuns/baseboard.h b/baseboard/honeybuns/baseboard.h
index 28ac467264..32ecf32d23 100644
--- a/baseboard/honeybuns/baseboard.h
+++ b/baseboard/honeybuns/baseboard.h
@@ -88,6 +88,36 @@
 #define CONFIG_BOARD_VERSION_CBI
 #define CONFIG_CMD_CBI
 
+/* USB Configuration */
+#define CONFIG_USB
+#define CONFIG_STREAM_USB
+#define CONFIG_USB_UPDATE
+#define CONFIG_USB_SERIALNO
+#define DEFAULT_SERIALNO "Uninitialized"
+#define CONFIG_MAC_ADDR
+#define DEFAULT_MAC_ADDR "Uninitialized"
+
+/* USB endpoint indexes (use define rather than enum to expand them) */
+#define USB_EP_CONTROL		0
+#define USB_EP_UPDATE		1
+#define USB_EP_COUNT		2
+
+#define USB_IFACE_UPDATE	0
+#define USB_IFACE_COUNT		1
+
+#ifndef __ASSEMBLER__
+/* USB string indexes */
+enum usb_strings {
+	USB_STR_DESC = 0,
+	USB_STR_VENDOR,
+	USB_STR_PRODUCT,
+	USB_STR_SERIALNO,
+	USB_STR_VERSION,
+	USB_STR_UPDATE_NAME,
+	USB_STR_COUNT
+};
+#endif
+
 /* RW Specific Config Options */
 #ifdef SECTION_IS_RW
 
@@ -108,7 +138,6 @@
 #define CONFIG_USB_PD_TCPM_STM32GX
 #define CONFIG_USB_PD_TCPM_TCPCI
 #define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_PID 0x5048
 
 #define CONFIG_USB_PD_VBUS_DETECT_PPC
 #define CONFIG_USB_PD_DISCHARGE_PPC
@@ -162,9 +191,6 @@
 /* I2C Bus Configuration */
 #define CONFIG_I2C
 #define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_USBC		0
-#define I2C_PORT_MST		1
-#define I2C_PORT_EEPROM	2
 
 /*
  * Macros for GPIO signals used in common code that don't match the
@@ -197,6 +223,8 @@ enum adc_channel {
 extern const struct power_seq board_power_seq[];
 extern const size_t board_power_seq_count;
 
+int baseboard_usbc_init(int port);
+
 #endif /* !__ASSEMBLER__ */
 
 #endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/honeybuns/build.mk b/baseboard/honeybuns/build.mk
index ca13fcff46..2868911925 100644
--- a/baseboard/honeybuns/build.mk
+++ b/baseboard/honeybuns/build.mk
@@ -8,3 +8,4 @@
 
 baseboard-y=baseboard.o
 baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
+baseboard-y+=usbc_support.o
diff --git a/baseboard/honeybuns/usbc_support.c b/baseboard/honeybuns/usbc_support.c
new file mode 100644
index 0000000000..baa22a65dc
--- /dev/null
+++ b/baseboard/honeybuns/usbc_support.c
@@ -0,0 +1,137 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* USBC functions for RO */
+
+#include "common.h"
+#include "console.h"
+#include "sn5s330.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "system.h"
+#include "timer.h"
+#include "usb_charge.h"
+#include "usb_pd_tcpm.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+#include "registers.h"
+#include "ucpd-stm32gx.h"
+
+
+static void baseboard_ucpd_apply_rd(int port)
+{
+	uint32_t cfgr1_reg;
+	uint32_t moder_reg;
+	uint32_t cr;
+
+	/* Ensure that clock to UCPD is enabled */
+	STM32_RCC_APB1ENR2 |= STM32_RCC_APB1ENR2_UPCD1EN;
+
+	/* Make sure CC1/CC2 pins PB4/PB6 are set for analog mode */
+	moder_reg = STM32_GPIO_MODER(GPIO_B);
+	moder_reg |= 0x3300;
+	STM32_GPIO_MODER(GPIO_B) = moder_reg;
+	/*
+	 * CFGR1 must be written when UCPD peripheral is disabled. Note that
+	 * disabling ucpd causes the peripheral to quit any ongoing activity and
+	 * sets all ucpd registers back their default values.
+	 */
+
+	cfgr1_reg = STM32_UCPD_CFGR1_PSC_CLK_VAL(UCPD_PSC_DIV - 1) |
+		STM32_UCPD_CFGR1_TRANSWIN_VAL(UCPD_TRANSWIN_CNT - 1) |
+		STM32_UCPD_CFGR1_IFRGAP_VAL(UCPD_IFRGAP_CNT - 1) |
+		STM32_UCPD_CFGR1_HBITCLKD_VAL(UCPD_HBIT_DIV - 1);
+	STM32_UCPD_CFGR1(port) = cfgr1_reg;
+
+	/* Enable ucpd  */
+	STM32_UCPD_CFGR1(port) |= STM32_UCPD_CFGR1_UCPDEN;
+
+	/* Apply Rd to both CC lines */
+	cr = STM32_UCPD_CR(port);
+	cr |= STM32_UCPD_CR_ANAMODE | STM32_UCPD_CR_CCENABLE_MASK;
+	STM32_UCPD_CR(port) = cr;
+
+	/*
+	 * After exiting reset, stm32gx will have dead battery mode enabled by
+	 * default which connects Rd to CC1/CC2. This should be disabled when EC
+	 * is powered up.
+	 */
+	STM32_PWR_CR3 |= STM32_PWR_CR3_UCPD1_DBDIS;
+}
+
+static int read_reg(uint8_t port, int reg, int *regval)
+{
+	return i2c_read8(ppc_chips[port].i2c_port,
+			 ppc_chips[port].i2c_addr_flags,
+			 reg,
+			 regval);
+}
+
+static int write_reg(uint8_t port, int reg, int regval)
+{
+	return i2c_write8(ppc_chips[port].i2c_port,
+			  ppc_chips[port].i2c_addr_flags,
+			  reg,
+			  regval);
+}
+
+static int baseboard_ppc_enable_sink_path(int port)
+{
+	int regval;
+	int status;
+	int retries;
+
+	/*
+	 * It seems that sometimes setting the FUNC_SET1 register fails
+	 * initially.  Therefore, we'll retry a couple of times.
+	 */
+	retries = 0;
+	do {
+		status = write_reg(port, SN5S330_FUNC_SET1, SN5S330_ILIM_3_06);
+		if (status) {
+			retries++;
+			msleep(1);
+		} else {
+			break;
+		}
+	} while (retries < 10);
+
+	/* Turn off dead battery resistors, turn on CC FETs */
+	status = read_reg(port, SN5S330_FUNC_SET4, &regval);
+	if (!status) {
+		regval |= SN5S330_CC_EN;
+		status = write_reg(port, SN5S330_FUNC_SET4, regval);
+	}
+	if (status) {
+		return status;
+	}
+
+	/* Enable sink path via PP2 */
+	status = read_reg(port, SN5S330_FUNC_SET3, &regval);
+	if (!status) {
+		regval &= ~SN5S330_PP1_EN;
+		regval |= SN5S330_PP2_EN;
+		status = write_reg(port, SN5S330_FUNC_SET3, regval);
+	}
+	if (status) {
+		return status;
+	}
+
+	return EC_SUCCESS;
+}
+
+int baseboard_usbc_init(int port)
+{
+	int rv;
+
+	/* Initialize ucpd and apply Rd to CC lines */
+	baseboard_ucpd_apply_rd(port);
+	/* Initialize ppc to enable sink path */
+	rv = baseboard_ppc_enable_sink_path(port);
+
+	return rv;
+}
+