diff options
| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2021-10-20 19:12:07 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-12-16 21:24:49 +0000 |
| commit | eaa6e6a4939437075f13d9f91beda09fd150b1cc (patch) | |
| tree | f52d0e623caca54eb90f46645c8d23cb0b01c498 /baseboard/intelrvp/README.md | |
| parent | 53080524f2fdc69a9a843f8e12b365c1388c1dd5 (diff) | |
| download | chrome-ec-eaa6e6a4939437075f13d9f91beda09fd150b1cc.tar.gz | |
intelrvp: Remove TGLRVP & JSLRVP boards and MECC0.9
As support for TGLRVP & JSLRVP has reached end of life remove these
boards and also support for MECC0.9 that applies only to TGLRVP &
JSLRVP.
BUG=none
BRANCH=none
TEST=make buildall -j
Cq-Include-Trybots: luci.chromeos.cq:cq-orchestrator
Change-Id: Ic2acb2e87c6db8395a9e8caeaedf130b9dbc3891
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3238255
Reviewed-by: Poornima Tom <poornima.tom@intel.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'baseboard/intelrvp/README.md')
| -rw-r--r-- | baseboard/intelrvp/README.md | 14 |
1 files changed, 1 insertions, 13 deletions
diff --git a/baseboard/intelrvp/README.md b/baseboard/intelrvp/README.md index 39286e130d..3405633132 100644 --- a/baseboard/intelrvp/README.md +++ b/baseboard/intelrvp/README.md @@ -10,25 +10,13 @@ baseboard code is applicable to Icelake and its successors only. Following hardware features are supported on MECC header by RVP and can be validated by software by MECC. -## MECC version 0.9 features - -1. Power to MECC is provided by RVP (battery + DC Jack + Type C) -2. Power control pins for Intel SOC are added -3. Servo V2 header need to be added by MECC -4. Google H1 chip need to be added by MECC (optional for EC vendors) -5. 2 Type-C port support (SRC/SNK/BC1.2/MUX/Rerimer) -6. 6 Temperature sensors -7. 4 ADC -8. 4 I2C Channels -9. 1 Fan control - ## MECC version 1.0 features 1. Power to MECC is provided by RVP (battery + DC Jack + Type C) 2. Power control pins for Intel SOC are added 3. Servo V2 header need to be added by MECC 4. Google H1 chip need to be added by MECC (optional for EC vendors) -5. 4 Type-C port support (SRC/SNK/BC1.2/MUX/Rerimer) as Add In Card (AIC) on +5. 4 Type-C port support (SRC/SNK/MUX/Rerimer) as Add In Card (AIC) on RVP 6. Optional 2 Type-C port routed to MECC for integrated TCPC support 7. 6 I2C Channels |