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| author | Poornima Tom <poornima.tom@intel.com> | 2020-09-04 20:08:51 +0530 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-11-03 18:10:24 +0000 |
| commit | 3b96973d29dd794cce7d7a32d16e2f531b97203a (patch) | |
| tree | 2d890f2d83958010c03deb6ccc30ea005ae890bb /baseboard/intelrvp/ite_ec.c | |
| parent | ba9f1a8dd198b81fd7598326397c5c6dd746b808 (diff) | |
| download | chrome-ec-3b96973d29dd794cce7d7a32d16e2f531b97203a.tar.gz | |
ADLP-RVP: Config to enable TBT
BRANCH=None
BUG=b:171409539
TEST=Able to enter TBT mode
Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Change-Id: I81fb01ac9e537ded25cfffc8a9691c173ed41a49
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2490900
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Diffstat (limited to 'baseboard/intelrvp/ite_ec.c')
| -rw-r--r-- | baseboard/intelrvp/ite_ec.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/baseboard/intelrvp/ite_ec.c b/baseboard/intelrvp/ite_ec.c index 27a4138aa3..44ddf6d53e 100644 --- a/baseboard/intelrvp/ite_ec.c +++ b/baseboard/intelrvp/ite_ec.c @@ -105,6 +105,7 @@ BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT); #ifdef CONFIG_USBC_VCONN void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) { +#ifndef CONFIG_USBC_PPC_VCONN /* * Setting VCONN low by disabling the power switch before * enabling the VCONN on respective CC line @@ -119,5 +120,6 @@ void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled) tcpc_gpios[port].vconn.cc2_pin : tcpc_gpios[port].vconn.cc1_pin, tcpc_gpios[port].vconn.pin_pol); +#endif } #endif |