adlprvp: add Alderlake RVP support

Following features are enabled and verified.
   1. Power sequencing
   2. Host communication
   3. USB TYPE-C - TCPC over PD AIC
   4. H1 Close Case Debug
   5. LED
   6. Keyboard

BRANCH=None
BUG=b:169551130
TEST=Build, flash and boot the Alderlake RVP platform to OS
make BOARD=adlrvpp_ite -j;
sudo util/flash_ec --board=adlrvpp_ite --image=<path>

Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Change-Id: I9d85e0cb93bc94f042f902b73ebd96a354d0f365
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435177
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>

5 files changed, 198 insertions, 0 deletions

diff --git a/baseboard/intelrvp/README.md b/baseboard/intelrvp/README.md
index 00a0662ddb..2ecad4dd0c 100644
--- a/baseboard/intelrvp/README.md
+++ b/baseboard/intelrvp/README.md
@@ -25,3 +25,15 @@ MECC version 0.9 features
 7. 4 ADC
 8. 4 I2C Channels
 9. 1 Fan control
+
+MECC version 1.0 features
+1. Power to MECC is provide by RVP (battery + DC Jack + Type C)
+2. Power control pins for Intel SOC are added
+3. Servo V2 header need to be added by MECC
+4. Google H1 chip need to be added by MECC (optional for EC vendors)
+5. 4 Type-C port support (SRC/SNK/BC1.2/MUX/Rerimer) as Add In Card (AIC)
+   on RVP
+6. Optional 2 Type-C port routed to MECC for integrated TCPC support
+7. 6 I2C Channels
+8. 2 SMLINK Channels
+9. 2 I3C channels
diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h
index bb2c9c5cba..63eb9f919f 100644
--- a/baseboard/intelrvp/baseboard.h
+++ b/baseboard/intelrvp/baseboard.h
@@ -248,6 +248,14 @@ struct tcpc_gpio_config_t {
 };
 extern const struct tcpc_gpio_config_t tcpc_gpios[];
 
+struct tcpc_aic_gpio_config_t {
+	/* TCPC interrupt */
+	enum gpio_signal tcpc_alert;
+	/* PPC interrupt */
+	enum gpio_signal ppc_alert;
+};
+extern const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[];
+
 /* Reset PD MCU */
 void board_reset_pd_mcu(void);
 void board_charging_enable(int port, int enable);
diff --git a/baseboard/intelrvp/build.mk b/baseboard/intelrvp/build.mk
index e8d5c17b4a..cfa92cc0c6 100644
--- a/baseboard/intelrvp/build.mk
+++ b/baseboard/intelrvp/build.mk
@@ -15,6 +15,8 @@ ifneq ($(CONFIG_USB_POWER_DELIVERY),)
 baseboard-$(CONFIG_USB_POWER_DELIVERY)+=chg_usb_pd.o
 baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_0_9)+=chg_usb_pd_mecc_0_9.o
 baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_0_9)+=usb_pd_policy_mecc_0_9.o
+baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_1_0)+=chg_usb_pd_mecc_1_0.o
+baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_1_0)+=usb_pd_policy_mecc_1_0.o
 endif
 
 #EC specific files
diff --git a/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c b/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c
new file mode 100644
index 0000000000..639e7863a9
--- /dev/null
+++ b/baseboard/intelrvp/chg_usb_pd_mecc_1_0.c
@@ -0,0 +1,96 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel-RVP family-specific configuration */
+
+#include "charge_manager.h"
+#include "charge_state_v2.h"
+#include "console.h"
+#include "driver/ppc/sn5s330.h"
+#include "hooks.h"
+#include "tcpci.h"
+#include "system.h"
+#include "usbc_ppc.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+
+static void baseboard_tcpc_init(void)
+{
+	int i;
+
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		/* Enable PPC interrupts. */
+		gpio_enable_interrupt(tcpc_aic_gpios[i].ppc_alert);
+
+		/* Enable TCPC interrupts. */
+		if (tcpc_config[i].bus_type != EC_BUS_TYPE_EMBEDDED)
+			gpio_enable_interrupt(tcpc_aic_gpios[i].tcpc_alert);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_CHIPSET);
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		/* No alerts for embdeded TCPC */
+		if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED)
+			continue;
+
+		if (signal == tcpc_aic_gpios[i].tcpc_alert) {
+			schedule_deferred_pd_interrupt(i);
+			break;
+		}
+	}
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int i;
+
+	/* Check which port has the ALERT line set */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		/* No alerts for embdeded TCPC */
+		if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED)
+			continue;
+
+		if (!gpio_get_level(tcpc_aic_gpios[i].tcpc_alert))
+			status |= PD_STATUS_TCPC_ALERT_0 << i;
+	}
+
+	return status;
+}
+
+int ppc_get_alert_status(int port)
+{
+	return !gpio_get_level(tcpc_aic_gpios[port].ppc_alert);
+}
+
+/* PPC support routines */
+void ppc_interrupt(enum gpio_signal signal)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (signal == tcpc_aic_gpios[i].ppc_alert) {
+			sn5s330_interrupt(i);
+			break;
+		}
+	}
+}
+
+void board_charging_enable(int port, int enable)
+{
+	if (ppc_vbus_sink_enable(port, enable))
+		CPRINTS("C%d: sink path %s failed",
+				port, enable ? "en" : "dis");
+}
diff --git a/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c b/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c
new file mode 100644
index 0000000000..cdad0d3ca8
--- /dev/null
+++ b/baseboard/intelrvp/usb_pd_policy_mecc_1_0.c
@@ -0,0 +1,80 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "console.h"
+#include "gpio.h"
+#include "system.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	pd_set_vbus_discharge(port, 0);
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv)
+		return rv;
+
+#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
+	/* Ensure we advertise the proper available current quota */
+	charge_manager_source_port(port, 1);
+#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+void pd_power_supply_reset(int port)
+{
+	int prev_en;
+
+	prev_en = board_vbus_source_enabled(port);
+
+	/* Disable VBUS. */
+	ppc_vbus_source_enable(port, 0);
+
+	/* Enable discharge if we were previously sourcing 5V */
+	if (prev_en)
+		pd_set_vbus_discharge(port, 1);
+
+#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
+	/* Give back the current quota we are no longer using */
+	charge_manager_source_port(port, 0);
+#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_check_vconn_swap(int port)
+{
+	/* Only allow vconn swap if PP3300 rail is enabled */
+	return gpio_get_level(GPIO_EN_PP3300_A);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	return ppc_is_vbus_present(port);
+}
+
+int board_vbus_source_enabled(int port)
+{
+	return (port != DEDICATED_CHARGE_PORT && ppc_is_sourcing_vbus(port));
+}