intelrvp: Add support for NPCX EC configs

Added base code to support NPCX EC on Intel RVP. Respective board
files can reference these configs for easier integration.

BUG=b:181967246
BRANCH=none
TEST=make buildall -j

Change-Id: I4bf7570093c267ca4edb45d115585982f62d4623
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2770179
Reviewed-by: Poornima Tom <poornima.tom@intel.com>
Reviewed-by: caveh jalali <caveh@chromium.org>

4 files changed, 121 insertions, 2 deletions

diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h
index 7ec90f0507..6d6ebb4c2f 100644
--- a/baseboard/intelrvp/baseboard.h
+++ b/baseboard/intelrvp/baseboard.h
@@ -12,10 +12,12 @@
 
 #ifdef VARIANT_INTELRVP_EC_IT8320
 	#include "ite_ec.h"
-/* VARIANT_INTELRVP_EC_IT8320 */
 #elif defined(VARIANT_INTELRVP_EC_MCHP)
 	#include "mchp_ec.h"
-/* VARIANT_INTELRVP_EC_MCHP */
+#elif defined(VARIANT_INTELRVP_EC_NPCX)
+	#include "npcx_ec.h"
+#else
+	#error "Define EC chip variant"
 #endif
 
 /*
diff --git a/baseboard/intelrvp/build.mk b/baseboard/intelrvp/build.mk
index e3244a82f8..b7dbaa406b 100644
--- a/baseboard/intelrvp/build.mk
+++ b/baseboard/intelrvp/build.mk
@@ -21,6 +21,7 @@ endif
 #EC specific files
 baseboard-$(VARIANT_INTELRVP_EC_IT8320)+=ite_ec.o
 baseboard-$(VARIANT_INTELRVP_EC_MCHP)+=mchp_ec.o
+baseboard-$(VARIANT_INTELRVP_EC_NPCX)+=npcx_ec.o
 
 #BC1.2 specific files
 baseboard-$(CONFIG_BC12_DETECT_MAX14637)+=bc12.o
diff --git a/baseboard/intelrvp/npcx_ec.c b/baseboard/intelrvp/npcx_ec.c
new file mode 100644
index 0000000000..c48e202f87
--- /dev/null
+++ b/baseboard/intelrvp/npcx_ec.c
@@ -0,0 +1,78 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel BASEBOARD-RVP NPCX EC specific configuration */
+
+#include "adc_chip.h"
+#include "fan_chip.h"
+#include "keyboard_scan.h"
+#include "pwm_chip.h"
+#include "time.h"
+
+/* Keyboard scan setting */
+struct keyboard_scan_config keyscan_config = {
+	.output_settle_us = 35,
+	.debounce_down_us = 5 * MSEC,
+	.debounce_up_us = 40 * MSEC,
+	.scan_period_us = 3 * MSEC,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = 100 * MSEC,
+	.actual_key_mask = {
+		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SNS_AMBIENT] = {
+		.name = "ADC_TEMP_SNS_AMBIENT",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.input_ch = ADC_TEMP_SNS_AMBIENT_CHANNEL,
+	},
+	[ADC_TEMP_SNS_DDR] = {
+		.name = "ADC_TEMP_SNS_DDR",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.input_ch = ADC_TEMP_SNS_DDR_CHANNEL,
+	},
+	[ADC_TEMP_SNS_SKIN] = {
+		.name = "ADC_TEMP_SNS_SKIN",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.input_ch = ADC_TEMP_SNS_SKIN_CHANNEL,
+	},
+	[ADC_TEMP_SNS_VR] = {
+		.name = "ADC_TEMP_SNS_VR",
+		.factor_mul = ADC_MAX_MVOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+		.input_ch = ADC_TEMP_SNS_VR_CHANNEL,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* PWM configuration */
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_FAN] = {
+		.channel = PWN_FAN_CHANNEL,
+		.flags = 0,
+		.freq = 30000,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+const struct mft_t mft_channels[] = {
+	[MFT_CH_0] = {
+		.module = NPCX_MFT_MODULE_2,
+		.clk_src = TCKC_LFCLK,
+		.pwm_id = PWM_CH_FAN,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(mft_channels) == MFT_CH_COUNT);
diff --git a/baseboard/intelrvp/npcx_ec.h b/baseboard/intelrvp/npcx_ec.h
new file mode 100644
index 0000000000..52bcb2dae6
--- /dev/null
+++ b/baseboard/intelrvp/npcx_ec.h
@@ -0,0 +1,38 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel BASEBOARD-RVP NPCX EC specific configuration */
+
+#ifndef __CROS_EC_NPCX_EC_H
+#define __CROS_EC_NPCX_EC_H
+
+#if !defined(__ASSEMBLER__)
+
+enum mft_channel {
+	MFT_CH_0 = 0,
+	/* Number of MFT channels */
+	MFT_CH_COUNT,
+};
+
+#endif /* __ASSEMBLER__ */
+
+/* ADC channels */
+#define ADC_MAX_MVOLT			ADC_MAX_VOLT
+#define ADC_TEMP_SNS_AMBIENT_CHANNEL	NPCX_ADC_CH3
+#define ADC_TEMP_SNS_DDR_CHANNEL	NPCX_ADC_CH4
+#define ADC_TEMP_SNS_SKIN_CHANNEL	NPCX_ADC_CH2
+#define ADC_TEMP_SNS_VR_CHANNEL		NPCX_ADC_CH1
+
+/* KSO2 is inverted */
+#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
+
+/* Fan */
+#define CONFIG_PWM
+#define PWN_FAN_CHANNEL		3
+
+/* GPIO64/65 are used as UART pins. */
+#define NPCX_UART_MODULE2	1
+
+#endif /* __CROS_EC_NPCX_EC_H */