icelake: Cleanup power sequencing for IceLake/TigerLake/JasperLake

Configure PWROK generation related signals for Ice Lake, Tiger Lake, and
Jasper Lake SoCs. The array driven sequencing provides better
flexibility for the PWROK signals, some of which may be automatically
handled by the platform and some require EC control.

BUG=b:150726713
BRANCH=none
TEST=make buildall
TEST=Volteer: verify VCCIN enable and SYS_PWROK generation during S0 and
verify signals are deasserted when exiting S0.
TEST=Wadledoo: verified 2ms delay between ALL_SYS_PWRGD and PCH_PWROK,
verified JPL sequences to S0.

Change-Id: Iceae29c65398643839b31f6cd757352282849fda
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2088285
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>

1 files changed, 42 insertions, 10 deletions

diff --git a/baseboard/volteer/baseboard.c b/baseboard/volteer/baseboard.c
index 144d26b57c..47d0a955ba 100644
--- a/baseboard/volteer/baseboard.c
+++ b/baseboard/volteer/baseboard.c
@@ -23,6 +23,7 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "icelake.h"
 #include "keyboard_scan.h"
 #include "pwm.h"
 #include "pwm_chip.h"
@@ -176,6 +177,47 @@ const struct charger_config_t chg_chips[] = {
 
 const unsigned int chg_cnt = ARRAY_SIZE(chg_chips);
 
+/******************************************************************************/
+/*
+ * PWROK signal configuration, see the PWROK Generation Flow Diagram (Figure
+ * 235) in the Tiger Lake Platform Design Guide for the list of potential
+ * signals.
+ *
+ * Volteer uses this power sequence:
+ *	GPIO_EN_PPVAR_VCCIN - Turns on the VCCIN rail. Also used as a delay to
+ *		the VCCST_PWRGD input to the AP so this signal must be delayed
+ *		5 ms to meet the tCPU00 timing requirement.
+ *	GPIO_EC_PCH_SYS_PWROK - Asserts the SYS_PWROK input to the AP. Delayed
+ *		a total of 50 ms after ALL_SYS_PWRGD input is asserted. See
+ *		b/144478941 for full discussion.
+ *
+ * Volteer does not provide direct EC control for the VCCST_PWRGD and PCH_PWROK
+ * signals. If your board adds these signals to the EC, copy this array
+ * to your board.c file and modify as needed.
+ */
+const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {
+	{
+		.gpio = GPIO_EN_PPVAR_VCCIN,
+		.delay_ms = 5,
+	},
+	{
+		.gpio = GPIO_EC_PCH_SYS_PWROK,
+		.delay_ms = 50 - 5,
+	},
+};
+const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
+
+const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {
+	/* No delays needed during S0 exit */
+	{
+		.gpio = GPIO_EC_PCH_SYS_PWROK,
+	},
+	/* Turn off VCCIN last */
+	{
+		.gpio = GPIO_EN_PPVAR_VCCIN,
+	},
+};
+const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list);
 
 /******************************************************************************/
 /* PWM configuration */
@@ -636,16 +678,6 @@ void board_overcurrent_event(int port, int is_overcurrented)
 	/* TODO: b/140561826 - check correct operation for Volteer */
 }
 
-/*
- * Delay assertion of PCH_SYS_PWROK from assertion of the PG_EC_ALL_SYS_PWRGD
- * input. This ensures PCH_SYS_PWROK is asserted only after all rails have
- * stabilized. See b/144478941 for full discussion.
- */
-__override void board_icl_tgl_all_sys_pwrgood(void)
-{
-	msleep(50);
-}
-
 static void baseboard_init(void)
 {
 	/* Illuminate motherboard and daughter board LEDs equally to start. */