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| author | Sue Chen <sue.chen@quanta.corp-partner.google.com> | 2021-07-02 10:10:19 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-07-30 04:28:53 +0000 |
| commit | 05e69748e694ffe803ebc1422c25dda6dfc87d53 (patch) | |
| tree | 885168cdc53502afbe50565e9b7aaf76a96ef8a9 /baseboard/zork/cbi_ssfc.c | |
| parent | 94aa170edecde87bc8331021540a1f9692b21569 (diff) | |
| download | chrome-ec-05e69748e694ffe803ebc1422c25dda6dfc87d53.tar.gz | |
Ezkinil: Add PS8818 for TYPEC C1 secondary MUX
Use SSFC bits 6-7 to choose which secondary MUX is used.
BUG=b:192523667
BRANCH=zork
TEST=After setting SSFC to 0x80 on the DUT with PS8818,
the typec on DB works fine.
Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com>
Change-Id: I8a66098d1e9b947acfb26b78f0cec7f835bf4c40
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3000894
Reviewed-by: Edward Hill <ecgh@chromium.org>
Commit-Queue: Edward Hill <ecgh@chromium.org>
Diffstat (limited to 'baseboard/zork/cbi_ssfc.c')
| -rw-r--r-- | baseboard/zork/cbi_ssfc.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/baseboard/zork/cbi_ssfc.c b/baseboard/zork/cbi_ssfc.c index 3fad4cb9fe..1078ec6486 100644 --- a/baseboard/zork/cbi_ssfc.c +++ b/baseboard/zork/cbi_ssfc.c @@ -41,3 +41,8 @@ enum ec_ssfc_edp_phy_alt_tuning get_cbi_ssfc_edp_phy_alt_tuning(void) SSFC_EDP_PHY_ALT_TUNING_OFFSET; } +enum ec_ssfc_c1_mux get_cbi_ssfc_c1_mux(void) +{ + return (cached_ssfc & SSFC_C1_MUX_MASK) >> + SSFC_C1_MUX_OFFSET; +} |