baseboard/guybrush/baseboard.h: Format with clang-format

BUG=b:236386294
BRANCH=none
TEST=none

Change-Id: I35d80d5963edf5193b2e99fceaf261d52eacbfbd
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3727519
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>

1 files changed, 49 insertions, 62 deletions

diff --git a/baseboard/guybrush/baseboard.h b/baseboard/guybrush/baseboard.h
index 2e30dfcc27..96056acf5e 100644
--- a/baseboard/guybrush/baseboard.h
+++ b/baseboard/guybrush/baseboard.h
@@ -10,8 +10,8 @@
 
 /* NPCX9 config */
 #define CONFIG_PORT80_4_BYTE
-#define NPCX9_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
-#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
+#define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */
+#define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */
 
 /* Optional features */
 #define CONFIG_ASSERT_CCD_MODE_ON_DTS_CONNECT
@@ -32,8 +32,8 @@
 #define CONFIG_VBOOT_HASH
 #define CONFIG_VSTORE
 #define CONFIG_VSTORE_SLOT_COUNT 1
-#define GPIO_ENTERING_RW	GPIO_EC_ENTERING_RW
-#define GPIO_PACKET_MODE_EN	GPIO_EC_GSC_PACKET_MODE
+#define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW
+#define GPIO_PACKET_MODE_EN GPIO_EC_GSC_PACKET_MODE
 
 /* CBI Config */
 #define CONFIG_CBI_EEPROM
@@ -41,7 +41,7 @@
 
 /* Power Config */
 #define CONFIG_CHIPSET_X86_RSMRST_DELAY
-#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#undef CONFIG_EXTPOWER_DEBOUNCE_MS
 #define CONFIG_EXTPOWER_DEBOUNCE_MS 200
 #define CONFIG_EXTPOWER_GPIO
 #define CONFIG_HIBERNATE_PSL
@@ -54,19 +54,19 @@
 #define CONFIG_POWER_SLEEP_FAILURE_DETECTION
 #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
 #define G3_TO_PWRBTN_DELAY_MS 16
-#define GPIO_AC_PRESENT		GPIO_ACOK_OD
-#define GPIO_EN_PWR_A		GPIO_EN_PWR_S5
-#define GPIO_PCH_PWRBTN_L	GPIO_EC_SOC_PWR_BTN_L
-#define GPIO_PCH_RSMRST_L	GPIO_EC_SOC_RSMRST_L
-#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S3_S0I3_L
-#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
-#define GPIO_PCH_SLP_S5_L	GPIO_SLP_S5_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_SOC_PWR_GOOD
-#define GPIO_PCH_WAKE_L		GPIO_EC_SOC_WAKE_L
-#define GPIO_POWER_BUTTON_L	GPIO_MECH_PWR_BTN_ODL
-#define GPIO_S0_PGOOD		GPIO_PG_PCORE_S0_R_OD
-#define GPIO_S5_PGOOD		GPIO_PG_PWR_S5
-#define GPIO_SYS_RESET_L	GPIO_EC_SYS_RST_L
+#define GPIO_AC_PRESENT GPIO_ACOK_OD
+#define GPIO_EN_PWR_A GPIO_EN_PWR_S5
+#define GPIO_PCH_PWRBTN_L GPIO_EC_SOC_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L GPIO_EC_SOC_RSMRST_L
+#define GPIO_PCH_SLP_S0_L GPIO_SLP_S3_S0I3_L
+#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK GPIO_EC_SOC_PWR_GOOD
+#define GPIO_PCH_WAKE_L GPIO_EC_SOC_WAKE_L
+#define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL
+#define GPIO_S0_PGOOD GPIO_PG_PCORE_S0_R_OD
+#define GPIO_S5_PGOOD GPIO_PG_PWR_S5
+#define GPIO_SYS_RESET_L GPIO_EC_SYS_RST_L
 #define SAFE_RESET_VBUS_DELAY_MS 900
 #define SAFE_RESET_VBUS_MV 5000
 /*
@@ -86,12 +86,12 @@
 #define CONFIG_TEMP_SENSOR_SB_TSI
 #define CONFIG_THERMISTOR
 #define CONFIG_CPU_PROCHOT_ACTIVE_LOW
-#define GPIO_CPU_PROCHOT	GPIO_PROCHOT_ODL
+#define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL
 
 /* Flash Config */
 /* See config_chip-npcx9.h for SPI flash configuration */
 #undef CONFIG_SPI_FLASH /* Don't enable external flash interface */
-#define GPIO_WP_L			GPIO_EC_WP_L
+#define GPIO_WP_L GPIO_EC_WP_L
 
 /* Host communication */
 #define CONFIG_CMD_APTHROTTLE
@@ -99,7 +99,7 @@
 #define CONFIG_HOST_INTERFACE_ESPI
 #define CONFIG_MKBP_EVENT
 #define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
-#define GPIO_EC_INT_L		GPIO_EC_SOC_INT_L
+#define GPIO_EC_INT_L GPIO_EC_SOC_INT_L
 
 /* Chipset config */
 #define CONFIG_CHIPSET_CEZANNE
@@ -114,15 +114,15 @@
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_KEYBOARD_VIVALDI
 #define CONFIG_KBLIGHT_ENABLE_PIN
-#define GPIO_EN_KEYBOARD_BACKLIGHT	GPIO_EN_KB_BL
-#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
+#define GPIO_EN_KEYBOARD_BACKLIGHT GPIO_EN_KB_BL
+#define GPIO_KBD_KSO2 GPIO_EC_KSO_02_INV
 
 /* Sensors */
 #ifdef HAS_TASK_MOTIONSENSE
 
 #define CONFIG_TABLET_MODE
 #define CONFIG_GMR_TABLET_MODE
-#define GPIO_TABLET_MODE_L		GPIO_TABLET_MODE
+#define GPIO_TABLET_MODE_L GPIO_TABLET_MODE
 #define CONFIG_DYNAMIC_MOTION_SENSOR_COUNT
 #define CONFIG_LID_ANGLE
 #define CONFIG_LID_ANGLE_UPDATE
@@ -138,7 +138,7 @@
 
 /* Sensors without hardware FIFO are in forced mode */
 #define CONFIG_ACCEL_FORCE_MODE_MASK (1 << LID_ACCEL)
-#endif  /* HAS_TASK_MOTIONSENSE */
+#endif /* HAS_TASK_MOTIONSENSE */
 
 /* Backlight config */
 #define CONFIG_BACKLIGHT_LID
@@ -146,7 +146,7 @@
 #define GPIO_ENABLE_BACKLIGHT_L GPIO_EC_DISABLE_DISP_BL
 
 /* Battery Config */
-#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
+#define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL
 #define CONFIG_BATTERY_CUT_OFF
 #define CONFIG_BATTERY_FUEL_GAUGE
 #define CONFIG_BATTERY_REVIVE_DISCONNECT
@@ -172,7 +172,7 @@
  * CONFIG_CHARGER_LIMIT_* is not set, so there is no additional restriction on
  * Depthcharge to boot OS.
  */
-#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		65000
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON 65000
 
 /*
  * We would prefer to use CONFIG_CHARGE_RAMP_HW to enable legacy BC1.2 charging
@@ -226,8 +226,8 @@
 #define CONFIG_IO_EXPANDER_NCT38XX
 #define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT
 
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY 30000 /* us */
 
 /* USB-A config */
 #define USB_PORT_COUNT USBA_PORT_COUNT
@@ -260,21 +260,21 @@
 #define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
 #define CONFIG_I2C_CONTROLLER
 #define CONFIG_I2C_UPDATE_IF_CHANGED
-#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
-#define I2C_PORT_TCPC1		NPCX_I2C_PORT1_0
-#define I2C_PORT_BATTERY	NPCX_I2C_PORT2_0
-#define I2C_PORT_USB_MUX	NPCX_I2C_PORT3_0
-#define I2C_PORT_POWER		NPCX_I2C_PORT4_1
-#define I2C_PORT_CHARGER	I2C_PORT_POWER
-#define I2C_PORT_EEPROM		NPCX_I2C_PORT5_0
-#define I2C_PORT_SENSOR		NPCX_I2C_PORT6_1
-#define I2C_PORT_THERMAL_AP	NPCX_I2C_PORT7_0
-#define I2C_ADDR_EEPROM_FLAGS	0x50
+#define I2C_PORT_TCPC0 NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1 NPCX_I2C_PORT1_0
+#define I2C_PORT_BATTERY NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_MUX NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER NPCX_I2C_PORT4_1
+#define I2C_PORT_CHARGER I2C_PORT_POWER
+#define I2C_PORT_EEPROM NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR NPCX_I2C_PORT6_1
+#define I2C_PORT_THERMAL_AP NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS 0x50
 
 /* Volume Button Config */
 #define CONFIG_VOLUME_BUTTONS
-#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
-#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L GPIO_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L GPIO_VOLDN_BTN_ODL
 
 /* Fan Config */
 #define CONFIG_FANS FAN_CH_COUNT
@@ -290,30 +290,22 @@
 
 /* Power input signals */
 enum power_signal {
-	X86_SLP_S0_N,		/* SOC  -> SLP_S3_S0I3_L */
-	X86_SLP_S3_N,		/* SOC  -> SLP_S3_L */
-	X86_SLP_S5_N,		/* SOC  -> SLP_S5_L */
+	X86_SLP_S0_N, /* SOC  -> SLP_S3_S0I3_L */
+	X86_SLP_S3_N, /* SOC  -> SLP_S3_L */
+	X86_SLP_S5_N, /* SOC  -> SLP_S5_L */
 
-	X86_S0_PGOOD,		/* PMIC -> S0_PWROK_OD */
-	X86_S5_PGOOD,		/* PMIC -> S5_PWROK */
+	X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */
+	X86_S5_PGOOD, /* PMIC -> S5_PWROK */
 
 	/* Number of X86 signals */
 	POWER_SIGNAL_COUNT,
 };
 
 /* USB-C ports */
-enum usbc_port {
-	USBC_PORT_C0 = 0,
-	USBC_PORT_C1,
-	USBC_PORT_COUNT
-};
+enum usbc_port { USBC_PORT_C0 = 0, USBC_PORT_C1, USBC_PORT_COUNT };
 
 /* USB-A ports */
-enum usba_port {
-	USBA_PORT_A0 = 0,
-	USBA_PORT_A1,
-	USBA_PORT_COUNT
-};
+enum usba_port { USBA_PORT_A0 = 0, USBA_PORT_A1, USBA_PORT_COUNT };
 
 /* TMP112 sensors */
 enum tmp112_sensor {
@@ -322,12 +314,7 @@ enum tmp112_sensor {
 	TMP112_COUNT,
 };
 
-enum sensor_id {
-	LID_ACCEL,
-	BASE_ACCEL,
-	BASE_GYRO,
-	SENSOR_COUNT
-};
+enum sensor_id { LID_ACCEL, BASE_ACCEL, BASE_GYRO, SENSOR_COUNT };
 
 /* PWM Channels */
 enum pwm_channel {