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| author | Zhuohao Lee <zhuohao@chromium.org> | 2022-04-20 10:56:40 +0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-04-21 18:29:19 +0000 |
| commit | c9ffdb43039161bc13efde3134775a668ffe05f2 (patch) | |
| tree | 3d256d97ddad47102a9761f2dfff22134d6b93c0 /baseboard | |
| parent | 455aabd9a21c8d9e0528ef3dc31440444c6cafd4 (diff) | |
| download | chrome-ec-c9ffdb43039161bc13efde3134775a668ffe05f2.tar.gz | |
brask: add CONFIG_CHIPSET_X86_RSMRST_AFTER_S5
When we use C2D2 to program the AP firmware, we need to enable the
EN_S5_RAILS. However, the power sequence ic will deassert the
SEQ_EC_RSMRST_ODL and the EC will bypass the RSMRST to the PCH and
make the AP starting to run. To avoid the spi bus contention with the
C2D2 during ap spi flash, we add CONFIG_CHIPSET_X86_RSMRST_AFTER_S5
to avoid the RSMRST be passed to the PCH before the S5.
BUG=b:214495213
BRANCH=None
TEST=1. use C2D2 to flash the ap firmware
2. use CCD to flash the pa firmware
Change-Id: I82776ec9802e47e699b47a134c079148e7282e24
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3595411
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'baseboard')
| -rw-r--r-- | baseboard/brask/baseboard.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/baseboard/brask/baseboard.h b/baseboard/brask/baseboard.h index dd7be91500..375420ba41 100644 --- a/baseboard/brask/baseboard.h +++ b/baseboard/brask/baseboard.h @@ -71,6 +71,7 @@ #define CONFIG_POWER_S4_RESIDENCY #define CONFIG_POWER_SLEEP_FAILURE_DETECTION #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE +#define CONFIG_CHIPSET_X86_RSMRST_AFTER_S5 /* * TODO(b/191742284): When DAM enabled coreboot image is flashed on top of DAM |