waddledoo: Add JSL support

waddledoo is using the Intel Jasperlake chipset.  This commit enables
support for that chipset as well as adding the other related power
sequencing signals.  JSL uses the same chipset driver as ICL, but
waddledoo doesn't have a couple of the power good pins that the driver
assumes.  Therefore, waddledoo overrides these power good signals using
other logic.

BUG=b:147257114,b:146172102
BRANCH=None
TEST=`make -j BOARD=waddledoo`

Change-Id: Ib4baa7ff38a4f59f751ecb16c22522eda71b6f4f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1987837
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Diana Z <dzigterman@chromium.org>

2 files changed, 51 insertions, 0 deletions

diff --git a/baseboard/dedede/baseboard.c b/baseboard/dedede/baseboard.c
index 740236d45f..4e7087f263 100644
--- a/baseboard/dedede/baseboard.c
+++ b/baseboard/dedede/baseboard.c
@@ -5,8 +5,10 @@
 
 /* Dedede family-specific configuration */
 
+#include "adc.h"
 #include "common.h"
 #include "gpio.h"
+#include "intel_x86.h"
 
 /*
  * Dedede does not use hibernate wake pins, but the super low power "Z-state"
@@ -16,3 +18,25 @@
  */
 const enum gpio_signal hibernate_wake_pins[] = {};
 const int hibernate_wake_pins_used;
+
+__override int intel_x86_get_pg_ec_dsw_pwrok(void)
+{
+	/*
+	 * The PP3300_A rail is an input to generate DPWROK.  Assuming that
+	 * power is good if voltage is at least 80% of nominal level.
+	 */
+	return adc_read_channel(ADC_VSNS_PP3300_A) > 2640;
+}
+
+__override int intel_x86_get_pg_ec_all_sys_pwrgd(void)
+{
+	/*
+	 * ALL_SYS_PWRGD is an AND of both DRAM PGOOD and VCCST PGOOD.  Note
+	 * that this is an inverted power good; a low value means that the power
+	 * is good.  Therefore, we are assuming that power is good if voltage is
+	 * no more than 20% of nominal level.
+	 */
+	int vccst = adc_read_channel(ADC_VSNS_PP1050_ST_S);
+
+	return (vccst < 210) && gpio_get_level(GPIO_PG_DRAM_OD);
+}
diff --git a/baseboard/dedede/baseboard.h b/baseboard/dedede/baseboard.h
index c3167898f2..e4b54b2860 100644
--- a/baseboard/dedede/baseboard.h
+++ b/baseboard/dedede/baseboard.h
@@ -36,6 +36,31 @@
 #error "Must define a VARIANT_DEDEDE_EC!"
 #endif
 
+/*
+ * Remapping of schematic GPIO names to common GPIO names expected (hardcoded)
+ * in the EC code base.
+ */
+#define GPIO_CPU_PROCHOT      GPIO_EC_PROCHOT_ODL
+#define GPIO_EC_INT_L         GPIO_EC_AP_MKBP_INT_L
+#define GPIO_EN_PP5000        GPIO_EN_PP5000_U
+#define GPIO_ENTERING_RW      GPIO_EC_ENTERING_RW
+#define GPIO_PCH_DSW_PWROK    GPIO_EC_AP_DPWROK
+#define GPIO_PCH_PWRBTN_L     GPIO_EC_AP_PWR_BTN_ODL
+#define GPIO_PCH_RSMRST_L     GPIO_EC_AP_RSMRST_L
+#define GPIO_PCH_RTCRST       GPIO_EC_AP_RTCRST
+#define GPIO_PCH_SLP_S0_L     GPIO_SLP_S0_L
+#define GPIO_PCH_SLP_S3_L     GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S4_L     GPIO_SLP_S4_L
+#define GPIO_PCH_SYS_PWROK    GPIO_EC_AP_SYS_PWROK
+#define GPIO_PCH_WAKE_L       GPIO_EC_AP_WAKE_ODL
+#define GPIO_PG_EC_RSMRST_ODL GPIO_RSMRST_PWRGD_L
+#define GPIO_POWER_BUTTON_L   GPIO_H1_EC_PWR_BTN_ODL
+#define GPIO_RSMRST_L_PGOOD   GPIO_RSMRST_PWRGD_L
+#define GPIO_SYS_RESET_L      GPIO_SYS_RST_ODL
+#define GPIO_VOLUME_UP_L      GPIO_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L    GPIO_VOLDN_BTN_ODL
+#define GPIO_WP               GPIO_EC_WP_OD
+
 /* Common EC defines */
 
 /* EC Modules */
@@ -61,9 +86,11 @@
 
 /* SoC */
 #define CONFIG_BOARD_HAS_RTC_RESET
+#define CONFIG_CHIPSET_JASPERLAKE
 #define CONFIG_KEYBOARD_PROTOCOL_8042
 #define CONFIG_POWER_BUTTON
 #define CONFIG_POWER_BUTTON_X86
+#define CONFIG_POWER_COMMON
 
 
 #ifndef __ASSEMBLER__