icelake: Cleanup power sequencing for IceLake/TigerLake/JasperLake

Configure PWROK generation related signals for Ice Lake, Tiger Lake, and
Jasper Lake SoCs. The array driven sequencing provides better
flexibility for the PWROK signals, some of which may be automatically
handled by the platform and some require EC control.

BUG=b:150726713
BRANCH=none
TEST=make buildall
TEST=Volteer: verify VCCIN enable and SYS_PWROK generation during S0 and
verify signals are deasserted when exiting S0.
TEST=Wadledoo: verified 2ms delay between ALL_SYS_PWRGD and PCH_PWROK,
verified JPL sequences to S0.

Change-Id: Iceae29c65398643839b31f6cd757352282849fda
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2088285
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>

4 files changed, 111 insertions, 19 deletions

diff --git a/baseboard/dedede/baseboard.c b/baseboard/dedede/baseboard.c
index 9ff750785f..59c23f560a 100644
--- a/baseboard/dedede/baseboard.c
+++ b/baseboard/dedede/baseboard.c
@@ -13,6 +13,62 @@
 #include "hooks.h"
 #include "intel_x86.h"
 
+/******************************************************************************/
+/*
+ * PWROK signal configuration, see the PWROK Generation Flow Diagram in the
+ * Jasper Lake Platform Design Guide for the list of potential signals.
+ *
+ * Dedede boards use this PWROK sequence:
+ *	GPIO_ALL_SYS_PWRGD - turns on VCCIN rail
+ *	GPIO_EC_AP_VCCST_PWRGD_OD - asserts VCCST_PWRGD to AP, requires 2ms
+ *		delay from VCCST stable to meet the tCPU00 platform sequencing
+ *		timing
+ *	GPIO_EC_AP_PCH_PWROK_OD - asserts PMC_PCH_PWROK to the AP. Note that
+ *		PMC_PCH_PWROK is also gated by the IMVP9_VRRDY_OD output from
+ *		the VCCIN voltage rail controller.
+ *	GPIO_EC_AP_SYS_PWROK - asserts PMC_SYS_PWROK to the AP
+ *
+ * Both PMC_PCH_PWROK and PMC_SYS_PWROK signals must both be asserted before
+ * the Jasper Lake SoC deasserts PMC_RLTRST_N. The platform may deassert
+ * PMC_PCH_PWROK and PMC_SYS_PWROK in any order to optimize overall boot
+ * latency.
+ */
+const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {
+	{
+		.gpio = GPIO_ALL_SYS_PWRGD,
+	},
+	{
+		.gpio = GPIO_EC_AP_VCCST_PWRGD_OD,
+		.delay_ms = 2,
+	},
+	{
+		.gpio = GPIO_EC_AP_PCH_PWROK_OD,
+	},
+	{
+		.gpio = GPIO_EC_AP_SYS_PWROK,
+	},
+};
+const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
+
+const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {
+	/* No delays needed during S0 exit */
+	{
+		.gpio = GPIO_EC_AP_VCCST_PWRGD_OD,
+	},
+	{
+		.gpio = GPIO_EC_AP_PCH_PWROK_OD,
+	},
+	{
+		.gpio = GPIO_EC_AP_SYS_PWROK,
+	},
+	/* Turn off the VCCIN rail last */
+	{
+		.gpio = GPIO_ALL_SYS_PWRGD,
+	},
+};
+const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list);
+
+
 /*
  * Dedede does not use hibernate wake pins, but the super low power "Z-state"
  * instead in which the EC is powered off entirely.  Power will be restored to
@@ -61,14 +117,6 @@ __override int intel_x86_get_pg_ec_all_sys_pwrgd(void)
 		gpio_get_level(GPIO_PG_VCCIO_EXT_OD);
 }
 
-__override void board_jsl_all_sys_pwrgd(int value)
-{
-	/*
-	 * ALL_SYS_PWRGD is an AND of both DRAM PGOOD and VCCST PGOOD.
-	 */
-	gpio_set_level(GPIO_ALL_SYS_PWRGD, value);
-}
-
 __override int power_signal_get_level(enum gpio_signal signal)
 {
 	if (signal == GPIO_PG_EC_DSW_PWROK)
diff --git a/baseboard/dedede/baseboard.h b/baseboard/dedede/baseboard.h
index f4f2e0e9d3..a684002f65 100644
--- a/baseboard/dedede/baseboard.h
+++ b/baseboard/dedede/baseboard.h
@@ -88,7 +88,6 @@
 #define GPIO_PCH_SLP_S0_L	GPIO_SLP_S0_L
 #define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
 #define GPIO_PCH_SLP_S4_L	GPIO_SLP_S4_L
-#define GPIO_PCH_SYS_PWROK	GPIO_EC_AP_SYS_PWROK
 #define GPIO_PCH_WAKE_L		GPIO_EC_AP_WAKE_ODL
 #define GPIO_PG_EC_RSMRST_ODL	GPIO_RSMRST_PWRGD_L
 #define GPIO_POWER_BUTTON_L	GPIO_H1_EC_PWR_BTN_ODL
diff --git a/baseboard/dragonegg/baseboard.c b/baseboard/dragonegg/baseboard.c
index aa2ee875b7..e737530570 100644
--- a/baseboard/dragonegg/baseboard.c
+++ b/baseboard/dragonegg/baseboard.c
@@ -21,6 +21,7 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "icelake.h"
 #include "keyboard_scan.h"
 #include "power.h"
 #include "timer.h"
@@ -91,6 +92,18 @@ const struct charger_config_t chg_chips[] = {
 const unsigned int chg_cnt = ARRAY_SIZE(chg_chips);
 
 /******************************************************************************/
+/* PWROK signal configuration */
+/*
+ * On Dragonegg the ALL_SYS_PWRGD, VCCST_PWRGD, PCH_PWROK, and SYS_PWROK
+ * signals are handled by the board. No EC control needed.
+ */
+const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {};
+const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
+
+const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {};
+const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list);
+
+/******************************************************************************/
 /* Chipset callbacks/hooks */
 
 /* Called on AP S5 -> S3 transition */
diff --git a/baseboard/volteer/baseboard.c b/baseboard/volteer/baseboard.c
index 144d26b57c..47d0a955ba 100644
--- a/baseboard/volteer/baseboard.c
+++ b/baseboard/volteer/baseboard.c
@@ -23,6 +23,7 @@
 #include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
+#include "icelake.h"
 #include "keyboard_scan.h"
 #include "pwm.h"
 #include "pwm_chip.h"
@@ -176,6 +177,47 @@ const struct charger_config_t chg_chips[] = {
 
 const unsigned int chg_cnt = ARRAY_SIZE(chg_chips);
 
+/******************************************************************************/
+/*
+ * PWROK signal configuration, see the PWROK Generation Flow Diagram (Figure
+ * 235) in the Tiger Lake Platform Design Guide for the list of potential
+ * signals.
+ *
+ * Volteer uses this power sequence:
+ *	GPIO_EN_PPVAR_VCCIN - Turns on the VCCIN rail. Also used as a delay to
+ *		the VCCST_PWRGD input to the AP so this signal must be delayed
+ *		5 ms to meet the tCPU00 timing requirement.
+ *	GPIO_EC_PCH_SYS_PWROK - Asserts the SYS_PWROK input to the AP. Delayed
+ *		a total of 50 ms after ALL_SYS_PWRGD input is asserted. See
+ *		b/144478941 for full discussion.
+ *
+ * Volteer does not provide direct EC control for the VCCST_PWRGD and PCH_PWROK
+ * signals. If your board adds these signals to the EC, copy this array
+ * to your board.c file and modify as needed.
+ */
+const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {
+	{
+		.gpio = GPIO_EN_PPVAR_VCCIN,
+		.delay_ms = 5,
+	},
+	{
+		.gpio = GPIO_EC_PCH_SYS_PWROK,
+		.delay_ms = 50 - 5,
+	},
+};
+const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
+
+const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {
+	/* No delays needed during S0 exit */
+	{
+		.gpio = GPIO_EC_PCH_SYS_PWROK,
+	},
+	/* Turn off VCCIN last */
+	{
+		.gpio = GPIO_EN_PPVAR_VCCIN,
+	},
+};
+const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_deassert_list);
 
 /******************************************************************************/
 /* PWM configuration */
@@ -636,16 +678,6 @@ void board_overcurrent_event(int port, int is_overcurrented)
 	/* TODO: b/140561826 - check correct operation for Volteer */
 }
 
-/*
- * Delay assertion of PCH_SYS_PWROK from assertion of the PG_EC_ALL_SYS_PWRGD
- * input. This ensures PCH_SYS_PWROK is asserted only after all rails have
- * stabilized. See b/144478941 for full discussion.
- */
-__override void board_icl_tgl_all_sys_pwrgood(void)
-{
-	msleep(50);
-}
-
 static void baseboard_init(void)
 {
 	/* Illuminate motherboard and daughter board LEDs equally to start. */