diff options
| author | Rob Barnes <robbarnes@google.com> | 2021-01-06 15:28:29 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-01-13 00:09:50 +0000 |
| commit | 527c905d0709f2310c428159b9e403de2946c6de (patch) | |
| tree | 4fe73a1ab05a5cdfc3db3330a3cf7cbe0d68ee6b /baseboard | |
| parent | 4517a8631ddcf1837423da6e793187a4cb5b291b (diff) | |
| download | chrome-ec-527c905d0709f2310c428159b9e403de2946c6de.tar.gz | |
guybrush: Implement board_hibernate
Implement board_hibernate with OVLO workaround.
BUG=None
BRANCH=None
TEST=Build
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I320809c2628686abfadd23693af82dd683ef9601
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613732
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Diffstat (limited to 'baseboard')
| -rw-r--r-- | baseboard/guybrush/baseboard.c | 19 | ||||
| -rw-r--r-- | baseboard/guybrush/baseboard.h | 2 |
2 files changed, 21 insertions, 0 deletions
diff --git a/baseboard/guybrush/baseboard.c b/baseboard/guybrush/baseboard.c index 12916ba4ef..ab1b092b9a 100644 --- a/baseboard/guybrush/baseboard.c +++ b/baseboard/guybrush/baseboard.c @@ -633,3 +633,22 @@ void board_pwrbtn_to_pch(int level) } gpio_set_level(GPIO_PCH_PWRBTN_L, level); } + +void board_hibernate(void) +{ + int port; + + /* + * If we are charging, then drop the Vbus level down to 5V to ensure + * that we don't get locked out of the 6.8V OVLO for our PPCs in + * dead-battery mode. This is needed when the TCPC/PPC rails go away. + * (b/79218851, b/143778351, b/147007265) + */ + port = charge_manager_get_active_charge_port(); + if (port != CHARGE_PORT_NONE) { + pd_request_source_voltage(port, SAFE_RESET_VBUS_MV); + + /* Give PD task and PPC chip time to get to 5V */ + msleep(SAFE_RESET_VBUS_DELAY_MS); + } +} diff --git a/baseboard/guybrush/baseboard.h b/baseboard/guybrush/baseboard.h index fc9ddee9d2..8ee64db72a 100644 --- a/baseboard/guybrush/baseboard.h +++ b/baseboard/guybrush/baseboard.h @@ -32,6 +32,8 @@ #define CONFIG_POWER_BUTTON_X86 #define CONFIG_POWER_BUTTON_TO_PCH_CUSTOM #define G3_TO_PWRBTN_DELAY_MS 80 +#define SAFE_RESET_VBUS_MV 5000 +#define SAFE_RESET_VBUS_DELAY_MS 900 #define GPIO_AC_PRESENT GPIO_ACOK_OD #define GPIO_POWER_BUTTON_L GPIO_MECH_PWR_BTN_ODL #define GPIO_PCH_PWRBTN_L GPIO_EC_SOC_PWR_BTN_L |