adlrvp: cleanup: Move common files to baseboard

Moved the ADLRVP specific common files to baseboard so that the
RVP variants with multiple MECC clients can leverage these files
without copying them over to board files.

BUG=none
BRANCH=none
TEST=make buildall -j

Change-Id: I19739a189aa29c198422f1e2013d59f5da97b02f
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2706259
Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.com>
Reviewed-by: Poornima Tom <poornima.tom@intel.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>

4 files changed, 523 insertions, 0 deletions

diff --git a/baseboard/intelrvp/adlrvp.c b/baseboard/intelrvp/adlrvp.c
new file mode 100644
index 0000000000..a9aac4eb0a
--- /dev/null
+++ b/baseboard/intelrvp/adlrvp.c
@@ -0,0 +1,325 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADLRVP board-specific common configuration */
+
+#include "bb_retimer.h"
+#include "charger.h"
+#include "common.h"
+#include "hooks.h"
+#include "isl9241.h"
+#include "pca9675.h"
+#include "power/icelake.h"
+#include "sn5s330.h"
+#include "system.h"
+#include "task.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args)
+
+/* TCPC AIC GPIO Configuration */
+const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = {
+	[TYPE_C_PORT_0] = {
+		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P0,
+		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P0,
+		.ppc_intr_handler = sn5s330_interrupt,
+	},
+	[TYPE_C_PORT_1] = {
+		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P1,
+		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P1,
+		.ppc_intr_handler = sn5s330_interrupt,
+	},
+#if defined(HAS_TASK_PD_C2)
+	[TYPE_C_PORT_2] = {
+		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P2,
+		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P2,
+		.ppc_intr_handler = sn5s330_interrupt,
+	},
+#endif
+#if defined(HAS_TASK_PD_C3)
+	[TYPE_C_PORT_3] = {
+		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P3,
+		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P3,
+		.ppc_intr_handler = sn5s330_interrupt,
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_aic_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/* USB-C PPC configuration */
+struct ppc_config_t ppc_chips[] = {
+	[TYPE_C_PORT_0] = {
+		.i2c_port = I2C_PORT_TYPEC_0,
+		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
+		.drv = &sn5s330_drv,
+	},
+	[TYPE_C_PORT_1] = {
+		.i2c_port = I2C_PORT_TYPEC_1,
+		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
+		.drv = &sn5s330_drv
+	},
+#if defined(HAS_TASK_PD_C2)
+	[TYPE_C_PORT_2] = {
+		.i2c_port = I2C_PORT_TYPEC_2,
+		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
+		.drv = &sn5s330_drv,
+	},
+#endif
+#if defined(HAS_TASK_PD_C3)
+	[TYPE_C_PORT_3] = {
+		.i2c_port = I2C_PORT_TYPEC_3,
+		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
+		.drv = &sn5s330_drv,
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT);
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+/* USB-C retimer Configuration */
+struct usb_mux usbc0_tcss_usb_mux = {
+	.usb_port = TYPE_C_PORT_0,
+	.driver = &virtual_usb_mux_driver,
+	.hpd_update = &virtual_hpd_update,
+};
+struct usb_mux usbc1_tcss_usb_mux = {
+	.usb_port = TYPE_C_PORT_1,
+	.driver = &virtual_usb_mux_driver,
+	.hpd_update = &virtual_hpd_update,
+};
+#if defined(HAS_TASK_PD_C2)
+struct usb_mux usbc2_tcss_usb_mux = {
+	.usb_port = TYPE_C_PORT_2,
+	.driver = &virtual_usb_mux_driver,
+	.hpd_update = &virtual_hpd_update,
+};
+#endif
+#if defined(HAS_TASK_PD_C3)
+struct usb_mux usbc3_tcss_usb_mux = {
+	.usb_port = TYPE_C_PORT_3,
+	.driver = &virtual_usb_mux_driver,
+	.hpd_update = &virtual_hpd_update,
+};
+#endif
+
+/* USB muxes Configuration */
+const struct usb_mux usb_muxes[] = {
+	[TYPE_C_PORT_0] = {
+		.usb_port = TYPE_C_PORT_0,
+		.next_mux = &usbc0_tcss_usb_mux,
+		.driver = &bb_usb_retimer,
+		.i2c_port = I2C_PORT_TYPEC_0,
+		.i2c_addr_flags = I2C_PORT0_BB_RETIMER_ADDR,
+	},
+	[TYPE_C_PORT_1] = {
+		.usb_port = TYPE_C_PORT_1,
+		.next_mux = &usbc1_tcss_usb_mux,
+		.driver = &bb_usb_retimer,
+		.i2c_port = I2C_PORT_TYPEC_1,
+		.i2c_addr_flags = I2C_PORT1_BB_RETIMER_ADDR,
+	},
+#if defined(HAS_TASK_PD_C2)
+	[TYPE_C_PORT_2] = {
+		.usb_port = TYPE_C_PORT_2,
+		.next_mux = &usbc2_tcss_usb_mux,
+		.driver = &bb_usb_retimer,
+		.i2c_port = I2C_PORT_TYPEC_2,
+		.i2c_addr_flags = I2C_PORT2_BB_RETIMER_ADDR,
+	},
+#endif
+#if defined(HAS_TASK_PD_C3)
+	[TYPE_C_PORT_3] = {
+		.usb_port = TYPE_C_PORT_3,
+		.next_mux = &usbc3_tcss_usb_mux,
+		.driver = &bb_usb_retimer,
+		.i2c_port = I2C_PORT_TYPEC_3,
+		.i2c_addr_flags = I2C_PORT3_BB_RETIMER_ADDR,
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/* Each TCPC have corresponding IO expander */
+const struct pca9675_ioexpander pca9675_iox[] = {
+	[TYPE_C_PORT_0] = {
+		.i2c_host_port = I2C_PORT_TYPEC_0,
+		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
+		.io_direction = TCPC_AIC_IOE_DIRECTION,
+	},
+	[TYPE_C_PORT_1] = {
+		.i2c_host_port = I2C_PORT_TYPEC_1,
+		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
+		.io_direction = TCPC_AIC_IOE_DIRECTION,
+	},
+#if defined(HAS_TASK_PD_C2)
+	[TYPE_C_PORT_2] = {
+		.i2c_host_port = I2C_PORT_TYPEC_2,
+		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
+		.io_direction = TCPC_AIC_IOE_DIRECTION,
+	},
+#endif
+#if defined(HAS_TASK_PD_C3)
+	[TYPE_C_PORT_3] = {
+		.i2c_host_port = I2C_PORT_TYPEC_3,
+		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
+		.io_direction = TCPC_AIC_IOE_DIRECTION,
+	},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(pca9675_iox) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/* Charger Chips */
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
+		.drv = &isl9241_drv,
+	},
+};
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	/* Port 0 & 1 and 2 & 3 share same line for over current indication */
+	/* If PD_C2 task is defined, PD_C3 task is assumed to be defined. */
+#if defined(HAS_TASK_PD_C2)
+	int ioex = port < TYPE_C_PORT_2 ?
+			TYPE_C_PORT_1 : TYPE_C_PORT_3;
+#else
+	int ioex = TYPE_C_PORT_1;
+#endif
+
+	if (is_overcurrented)
+		pca9675_update_pins(ioex, TCPC_AIC_IOE_OC, 0);
+	else
+		pca9675_update_pins(ioex, 0, TCPC_AIC_IOE_OC);
+}
+
+__override void bb_retimer_power_handle(const struct usb_mux *me, int on_off)
+{
+	/* Handle retimer's power domain.*/
+	if (on_off) {
+		pca9675_update_pins(me->usb_port,
+				TCPC_AIC_IOE_BB_RETIMER_LS_EN, 0);
+
+		/*
+		 * Tpw, minimum time from VCC to RESET_N de-assertion is 100us
+		 * For boards that don't provide a load switch control, the
+		 * retimer_init() function ensures power is up before calling
+		 * this function.
+		 */
+		msleep(1);
+		pca9675_update_pins(me->usb_port,
+				TCPC_AIC_IOE_BB_RETIMER_RST, 0);
+
+		/* Allow 1ms time for the retimer to power up lc_domain
+		 * which powers I2C controller within retimer
+		 */
+		msleep(1);
+
+	} else {
+		pca9675_update_pins(me->usb_port,
+				0, TCPC_AIC_IOE_BB_RETIMER_RST);
+		msleep(1);
+		pca9675_update_pins(me->usb_port,
+				0, TCPC_AIC_IOE_BB_RETIMER_LS_EN);
+	}
+}
+
+static void board_connect_c0_sbu_deferred(void)
+{
+	int ccd_intr_level = gpio_get_level(GPIO_CCD_MODE_ODL);
+
+	if (ccd_intr_level) {
+		/* Default set the SBU lines to AUX mode on TCPC-AIC */
+		pca9675_update_pins(TYPE_C_PORT_0, 0,
+			TCPC_AIC_IOE_USB_MUX_CNTRL_1 |
+			TCPC_AIC_IOE_USB_MUX_CNTRL_0);
+	} else {
+		/* Set the SBU lines to CCD mode on TCPC-AIC */
+		pca9675_update_pins(TYPE_C_PORT_0,
+			TCPC_AIC_IOE_USB_MUX_CNTRL_1,
+			TCPC_AIC_IOE_USB_MUX_CNTRL_0);
+	}
+}
+DECLARE_DEFERRED(board_connect_c0_sbu_deferred);
+
+void board_connect_c0_sbu(enum gpio_signal s)
+{
+	hook_call_deferred(&board_connect_c0_sbu_deferred_data, 0);
+}
+
+static void enable_h1_irq(void)
+{
+	gpio_enable_interrupt(GPIO_CCD_MODE_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, enable_h1_irq, HOOK_PRIO_LAST);
+
+static void tcpc_aic_init(void)
+{
+	int i;
+
+	/* Initialize the IOEXPANDER on TCPC-AIC */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		pca9675_init(i);
+
+	/* Default set the SBU lines to AUX mode on both the TCPC-AIC */
+	board_connect_c0_sbu_deferred();
+
+#if defined(HAS_TASK_PD_C2)
+	 /* Only TCPC-0 can do CCD or BSSB, Default set SBU lines to AUX */
+	pca9675_update_pins(TYPE_C_PORT_2, 0,
+		TCPC_AIC_IOE_USB_MUX_CNTRL_1 | TCPC_AIC_IOE_USB_MUX_CNTRL_0);
+#endif
+}
+DECLARE_HOOK(HOOK_INIT, tcpc_aic_init, HOOK_PRIO_INIT_PCA9675);
+
+/******************************************************************************/
+/* PWROK signal configuration */
+/*
+ * On ADLRVP, SYS_PWROK_EC is an output controlled by EC and uses ALL_SYS_PWRGD
+ * as input.
+ */
+const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {
+	{
+		.gpio = GPIO_SYS_PWROK_EC,
+		.delay_ms = 3,
+	},
+};
+const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
+
+const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {
+	{
+		.gpio = GPIO_SYS_PWROK_EC,
+	},
+};
+const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list);
+
+/*
+ * Returns board information (board id[7:0] and Fab id[15:8]) on success
+ * -1 on error.
+ */
+int board_get_version(void)
+{
+	int port0, port1;
+	int fab_id, board_id, bom_id;
+
+	if (ioexpander_read_intelrvp_version(&port0, &port1))
+		return -1;
+	/*
+	 * Port0: bit 0   - BOM ID(2)
+	 *        bit 2:1 - FAB ID(1:0) + 1
+	 * Port1: bit 7:6 - BOM ID(1:0)
+	 *        bit 5:0 - BOARD ID(5:0)
+	 */
+	bom_id = ((port1 & 0xC0) >> 6) | ((port0 & 0x01) << 2);
+	fab_id = ((port0 & 0x06) >> 1) + 1;
+	board_id = port1 & 0x3F;
+
+	CPRINTS("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id);
+
+	return board_id | (fab_id << 8);
+}
diff --git a/baseboard/intelrvp/adlrvp.h b/baseboard/intelrvp/adlrvp.h
new file mode 100644
index 0000000000..f87a235a4b
--- /dev/null
+++ b/baseboard/intelrvp/adlrvp.h
@@ -0,0 +1,144 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADL-RVP specific configuration */
+
+#ifndef __ADLRVP_BOARD_H
+#define __ADLRVP_BOARD_H
+
+/* Temperature sensor */
+#define CONFIG_TEMP_SENSOR
+
+#include "baseboard.h"
+
+/* MECC config */
+#define CONFIG_INTEL_RVP_MECC_VERSION_1_0
+
+/* Support early firmware selection */
+#define CONFIG_VBOOT_EFS2
+
+/* Chipset */
+#define CONFIG_CHIPSET_ALDERLAKE
+
+/* USB PD config */
+#if defined(HAS_TASK_PD_C2) && defined(HAS_TASK_PD_C3)
+#define CONFIG_USB_PD_PORT_MAX_COUNT 4
+#else
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#endif
+#define CONFIG_USB_MUX_VIRTUAL
+#define PD_MAX_POWER_MW              100000
+
+/* TCPC AIC config */
+/* Support NXP PCA9675 I/O expander. */
+#define CONFIG_IO_EXPANDER_PCA9675
+#define I2C_ADDR_PCA9675_TCPC_AIC_IOEX	0x21
+#define CONFIG_IO_EXPANDER_PORT_COUNT CONFIG_USB_PD_PORT_MAX_COUNT
+
+/* DC Jack charge ports */
+#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
+#define DEDICATED_CHARGE_PORT CONFIG_USB_PD_PORT_MAX_COUNT
+
+/* PPC */
+#define CONFIG_USBC_PPC_SN5S330
+#define CONFIG_USB_PD_VBUS_DETECT_PPC
+#define CONFIG_USB_PD_DISCHARGE_PPC
+#define I2C_ADDR_SN5S330_TCPC_AIC_PPC	0x40
+
+/* TCPC */
+#define CONFIG_USB_PD_DISCHARGE
+#define CONFIG_USB_PD_TCPM_FUSB302
+#define I2C_ADDR_FUSB302_TCPC_AIC	0x22
+
+/* Config BB retimer */
+#define CONFIG_USBC_RETIMER_INTEL_BB
+#define I2C_PORT0_BB_RETIMER_ADDR	0x56
+#define I2C_PORT1_BB_RETIMER_ADDR	0x57
+#if defined(HAS_TASK_PD_C2)
+#define I2C_PORT2_BB_RETIMER_ADDR	0x58
+#endif
+#if defined(HAS_TASK_PD_C3)
+#define I2C_PORT3_BB_RETIMER_ADDR	0x59
+#endif
+
+/* Enable VCONN */
+#define CONFIG_USBC_VCONN
+#define CONFIG_USBC_VCONN_SWAP
+
+/* Enabling Thunderbolt-compatible mode */
+#define CONFIG_USB_PD_TBT_COMPAT_MODE
+
+/* Enabling USB4 mode */
+#define CONFIG_USB_PD_USB4
+
+/* Config Fan */
+#define CONFIG_FANS		1
+#define BOARD_FAN_MIN_RPM	3000
+#define BOARD_FAN_MAX_RPM	10000
+
+/*
+ * TCPC AIC used on all the ports are identical expect the I2C lines which
+ * are on the respective TCPC port's EC I2C line. Hence, I2C address and
+ * the GPIOs to control the retimers are also same for all the ports.
+ */
+#define TCPC_AIC_IOE_BB_RETIMER_RST	PCA9675_IO_P00
+#define TCPC_AIC_IOE_BB_RETIMER_LS_EN	PCA9675_IO_P01
+#define TCPC_AIC_IOE_USB_MUX_CNTRL_1	PCA9675_IO_P04
+#define TCPC_AIC_IOE_USB_MUX_CNTRL_0	PCA9675_IO_P05
+#define TCPC_AIC_IOE_OC			PCA9675_IO_P10
+
+#define TCPC_AIC_IOE_DIRECTION (PCA9675_DEFAULT_IO_DIRECTION & \
+	~(TCPC_AIC_IOE_BB_RETIMER_RST | TCPC_AIC_IOE_BB_RETIMER_LS_EN | \
+	TCPC_AIC_IOE_USB_MUX_CNTRL_1 | TCPC_AIC_IOE_USB_MUX_CNTRL_0 | \
+	TCPC_AIC_IOE_OC))
+
+/* Charger */
+#define CONFIG_CHARGER_ISL9241
+
+/* Port 80 */
+#define PORT80_I2C_ADDR		MAX695X_I2C_ADDR1_FLAGS
+
+/* Board Id */
+#define I2C_ADDR_PCA9555_BOARD_ID_GPIO	0x22
+
+/*
+ * Frequent watchdog timer resets are seen, with the
+ * increase in number of type-c ports. So increase
+ * the timer value to support more type-c ports.
+ */
+#if defined(HAS_TASK_PD_C2) && defined(HAS_TASK_PD_C3)
+#undef CONFIG_WATCHDOG_PERIOD_MS
+#define CONFIG_WATCHDOG_PERIOD_MS 4000
+#endif
+
+#ifndef __ASSEMBLER__
+
+enum adlrvp_charge_ports {
+	TYPE_C_PORT_0,
+	TYPE_C_PORT_1,
+#if defined(HAS_TASK_PD_C2)
+	TYPE_C_PORT_2,
+#endif
+#if defined(HAS_TASK_PD_C3)
+	TYPE_C_PORT_3,
+#endif
+};
+
+enum battery_type {
+	BATTERY_GETAC_SMP_HHP_408,
+	BATTERY_TYPE_COUNT,
+};
+
+void espi_reset_pin_asserted_interrupt(enum gpio_signal signal);
+void extpower_interrupt(enum gpio_signal signal);
+void ppc_interrupt(enum gpio_signal signal);
+void tcpc_alert_event(enum gpio_signal signal);
+void board_connect_c0_sbu(enum gpio_signal s);
+int board_get_version(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __ADLRVP_BOARD_H */
diff --git a/baseboard/intelrvp/adlrvp_battery.c b/baseboard/intelrvp/adlrvp_battery.c
new file mode 100644
index 0000000000..315d5c247e
--- /dev/null
+++ b/baseboard/intelrvp/adlrvp_battery.c
@@ -0,0 +1,48 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "battery_smart.h"
+#include "common.h"
+#include "util.h"
+
+const struct board_batt_params board_battery_info[] = {
+	/*
+	 * Getac Battery (Getac SMP-HHP-408) Information
+	 * Fuel gauge: BQ40Z50-R3
+	 */
+	[BATTERY_GETAC_SMP_HHP_408] = {
+		.fuel_gauge = {
+			.manuf_name = "Getac",
+			.ship_mode = {
+				.reg_addr = 0x00,
+				.reg_data = { 0x0010, 0x0010 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x6000,
+				.disconnect_val = 0x6000,
+			}
+		},
+		.batt_info = {
+			.voltage_max = 13050,        /* mV */
+			.voltage_normal = 11400,
+			.voltage_min = 9000,
+			.precharge_current = 256,   /* mA */
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 45,
+			.charging_min_c = 0,
+			.charging_max_c = 45,
+			.discharging_min_c = 0,
+			.discharging_max_c = 60,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_GETAC_SMP_HHP_408;
+
diff --git a/baseboard/intelrvp/build.mk b/baseboard/intelrvp/build.mk
index 2df42df47a..e3244a82f8 100644
--- a/baseboard/intelrvp/build.mk
+++ b/baseboard/intelrvp/build.mk
@@ -24,3 +24,9 @@ baseboard-$(VARIANT_INTELRVP_EC_MCHP)+=mchp_ec.o
 
 #BC1.2 specific files
 baseboard-$(CONFIG_BC12_DETECT_MAX14637)+=bc12.o
+
+#Common board specific files
+ifneq ($(filter y,$(BOARD_ADLRVPP_ITE) $(BOARD_ADLRVPM_ITE)),)
+baseboard-y+=adlrvp.o
+baseboard-$(CONFIG_BATTERY_SMART)+=adlrvp_battery.o
+endif