hatch: Add support for power sequencing

This CL adds config options, board specific functions and GPIO signals
required to add power sequencing support.

BRANCH=none
BUG=b:122251649
TEST=make buildall, verified at factory that AP reaches S0

Change-Id: I5c7e8331b0f46a830b6e0f6722e7b05ba05212cb
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1377571
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>

2 files changed, 103 insertions, 1 deletions

diff --git a/baseboard/hatch/baseboard.c b/baseboard/hatch/baseboard.c
index 19de9d6cf5..035efa4395 100644
--- a/baseboard/hatch/baseboard.c
+++ b/baseboard/hatch/baseboard.c
@@ -4,9 +4,20 @@
  */
 
 /* Hatch family-specific configuration */
-
+#include "chipset.h"
+#include "console.h"
+#include "espi.h"
 #include "gpio.h"
+#include "hooks.h"
 #include "i2c.h"
+#include "power.h"
+#include "tcpci.h"
+#include "timer.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+
 
 /******************************************************************************/
 /* I2C port map configuration */
@@ -19,3 +30,63 @@ const struct i2c_port_t i2c_ports[] = {
 	{"eeprom",  I2C_PORT_EEPROM,  100, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* power signal list. */
+const struct power_signal_info power_signal_list[] = {
+
+	[X86_SLP_S0_DEASSERTED] = {GPIO_SLP_S0_L,
+		POWER_SIGNAL_ACTIVE_HIGH | POWER_SIGNAL_DISABLE_AT_BOOT,
+		"SLP_S0_DEASSERTED"},
+#ifdef CONFIG_HOSTCMD_ESPI_VW_SIGNALS
+	[X86_SLP_S3_DEASSERTED] = {VW_SLP_S3_L, POWER_SIGNAL_ACTIVE_HIGH,
+				   "SLP_S3_DEASSERTED"},
+	[X86_SLP_S4_DEASSERTED] = {VW_SLP_S4_L, POWER_SIGNAL_ACTIVE_HIGH,
+				   "SLP_S4_DEASSERTED"},
+#else
+	[X86_SLP_S3_DEASSERTED] = {GPIO_SLP_S3_L, POWER_SIGNAL_ACTIVE_HIGH,
+				   "SLP_S3_DEASSERTED"},
+	[X86_SLP_S4_DEASSERTED] = {GPIO_SLP_S4_L, POWER_SIGNAL_ACTIVE_HIGH,
+				   "SLP_S4_DEASSERTED"},
+#endif
+	[X86_RSMRST_L_PGOOD] = {GPIO_PG_EC_RSMRST_L, POWER_SIGNAL_ACTIVE_HIGH,
+				"RSMRST_L_PGOOD"},
+	[PP5000_A_PGOOD] = {GPIO_PP5000_A_PG_OD, POWER_SIGNAL_ACTIVE_HIGH,
+			    "PP5000_A_PGOOD"},
+	[ALL_SYS_PGOOD] = {GPIO_PG_EC_ALL_SYS_PWRGD, POWER_SIGNAL_ACTIVE_HIGH,
+			   "ALL_SYS_PWRGD"}
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+/******************************************************************************/
+/* Chipset callbacks/hooks */
+
+/* Called on AP S5 -> S3 transition */
+static void baseboard_chipset_startup(void)
+{
+	/* TODD(b/122266850): Need to fill out this hook */
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_chipset_startup,
+	     HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0iX -> S0 transition */
+static void baseboard_chipset_resume(void)
+{
+	/* TODD(b/122266850): Need to fill out this hook */
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S0iX transition */
+static void baseboard_chipset_suspend(void)
+{
+	/* TODD(b/122266850): Need to fill out this hook */
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend,
+	     HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S5 transition */
+static void baseboard_chipset_shutdown(void)
+{
+	/* TODD(b/122266850): Need to fill out this hook */
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, baseboard_chipset_shutdown,
+	     HOOK_PRIO_DEFAULT);
diff --git a/baseboard/hatch/baseboard.h b/baseboard/hatch/baseboard.h
index 9fa7b54f62..a840911e8c 100644
--- a/baseboard/hatch/baseboard.h
+++ b/baseboard/hatch/baseboard.h
@@ -16,6 +16,19 @@
 #define CONFIG_SPI_FLASH_REGS
 #define CONFIG_SPI_FLASH_W25Q80 /* Internal SPI flash type. */
 
+/* Chipset config */
+#define CONFIG_CHIPSET_COMETLAKE
+#define CONFIG_CHIPSET_HAS_PRE_INIT_CALLBACK
+#define CONFIG_CHIPSET_RESET_HOOK
+#define CONFIG_EXTPOWER_GPIO
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_X86
+#define CONFIG_POWER_COMMON
+/* TODO(b/111155507): Don't enable SOiX for now */
+/* #define CONFIG_POWER_S0IX */
+/* #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
+
+
 /* I2C Bus Configuration */
 #define CONFIG_I2C
 #define CONFIG_I2C_MASTER
@@ -27,4 +40,22 @@
 #define I2C_PORT_EEPROM		NPCX_I2C_PORT7_0
 #define I2C_ADDR_EEPROM		0xA0
 
+#define PP5000_PGOOD_POWER_SIGNAL_MASK POWER_SIGNAL_MASK(PP5000_A_PGOOD)
+
+#ifndef __ASSEMBLER__
+
+enum power_signal {
+	X86_SLP_S0_DEASSERTED,
+	X86_SLP_S3_DEASSERTED,
+	X86_SLP_S4_DEASSERTED,
+	X86_RSMRST_L_PGOOD,
+	PP5000_A_PGOOD,
+	ALL_SYS_PGOOD,
+	/* Number of X86 signals */
+	POWER_SIGNAL_COUNT
+};
+
+
+#endif /* !__ASSEMBLER__ */
+
 #endif /* __CROS_EC_BASEBOARD_H */