Drop some obsolete boards

samus: AUE in M91, M92 pushed to stable already
samus_pd: samus pd chip
dragonegg: canceled
cheza: canceled
flapjack_scp: flapjack was canceled
atlas_ish: atlas shipped, but ish project canceled
sklrvp,glkrvp: these are pretty old intel reference boards and the
    portage overlays were already deleted ... assume nobody needs the
    EC firmware anymore either

BUG=none
BRANCH=none
TEST=buildall

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I794867ac82f37ffa2267e2e59ac02bc381688c57
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3069716
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>

5 files changed, 0 insertions, 728 deletions

diff --git a/baseboard/dragonegg/baseboard.c b/baseboard/dragonegg/baseboard.c
deleted file mode 100644
index acbeadcf32..0000000000
--- a/baseboard/dragonegg/baseboard.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* DragonEgg family-specific configuration */
-#include "charge_manager.h"
-#include "charge_state_v2.h"
-#include "chipset.h"
-#include "console.h"
-#include "driver/bc12/max14637.h"
-#include "driver/charger/bq25710.h"
-#include "driver/ppc/nx20p348x.h"
-#include "driver/ppc/sn5s330.h"
-#include "driver/ppc/syv682x.h"
-#include "driver/tcpm/it83xx_pd.h"
-#include "driver/tcpm/tcpci.h"
-#include "driver/tcpm/tcpm.h"
-#include "driver/tcpm/tusb422.h"
-#include "espi.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "keyboard_scan.h"
-#include "power.h"
-#include "power/icelake.h"
-#include "timer.h"
-#include "util.h"
-#include "tcpm/tcpci.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define USB_PD_PORT_ITE_0	0
-#define USB_PD_PORT_ITE_1	1
-#define USB_PD_PORT_TUSB422_2	2
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
-#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
-
-/******************************************************************************/
-/* Keyboard scan setting */
-__override struct keyboard_scan_config keyscan_config = {
-	/*
-	 * F3 key scan cycle completed but scan input is not
-	 * charging to logic high when EC start scan next
-	 * column for "T" key, so we set .output_settle_us
-	 * to 80us from 50us.
-	 */
-	.output_settle_us = 80,
-	.debounce_down_us = 9 * MSEC,
-	.debounce_up_us = 30 * MSEC,
-	.scan_period_us = 3 * MSEC,
-	.min_post_scan_delay_us = 1000,
-	.poll_timeout_us = 100 * MSEC,
-	.actual_key_mask = {
-		0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
-		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
-	},
-};
-
-/******************************************************************************/
-/* Wake up pins */
-const enum gpio_signal hibernate_wake_pins[] = {
-	GPIO_LID_OPEN,
-	GPIO_AC_PRESENT,
-	GPIO_POWER_BUTTON_L,
-};
-const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
-
-/* I2C port map configuration */
-/* TODO(b/111125177): Increase these speeds to 400 kHz and verify operation */
-const struct i2c_port_t i2c_ports[] = {
-	{"eeprom", IT83XX_I2C_CH_A, 100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
-	{"sensor", IT83XX_I2C_CH_B, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
-	{"usbc12",  IT83XX_I2C_CH_C, 100, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
-	{"usbc0",  IT83XX_I2C_CH_E, 100, GPIO_I2C4_SCL, GPIO_I2C4_SDA},
-	{"power",  IT83XX_I2C_CH_F, 100, GPIO_I2C5_SCL, GPIO_I2C5_SDA}
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Charger Chips */
-const struct charger_config_t chg_chips[] = {
-	{
-		.i2c_port = I2C_PORT_CHARGER,
-		.i2c_addr_flags = BQ25710_SMBUS_ADDR1_FLAGS,
-		.drv = &bq25710_drv,
-	},
-};
-
-/******************************************************************************/
-/* PWROK signal configuration */
-/*
- * On Dragonegg the ALL_SYS_PWRGD, VCCST_PWRGD, PCH_PWROK, and SYS_PWROK
- * signals are handled by the board. No EC control needed.
- */
-const struct intel_x86_pwrok_signal pwrok_signal_assert_list[] = {};
-const int pwrok_signal_assert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-const struct intel_x86_pwrok_signal pwrok_signal_deassert_list[] = {};
-const int pwrok_signal_deassert_count = ARRAY_SIZE(pwrok_signal_assert_list);
-
-/******************************************************************************/
-/* Chipset callbacks/hooks */
-
-/* Called on AP S5 -> S3 transition */
-static void baseboard_chipset_startup(void)
-{
-	/* TODD(b/111121615): Need to fill out this hook */
-}
-DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_chipset_startup,
-	     HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0iX -> S0 transition */
-static void baseboard_chipset_resume(void)
-{
-	/* TODD(b/111121615): Need to fill out this hook */
-	/* Enable display backlight. */
-	gpio_set_level(GPIO_EDP_BKTLEN_OD, 1);
-}
-DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT);
-
-/* Called on AP S0 -> S0iX transition */
-static void baseboard_chipset_suspend(void)
-{
-	/* TODD(b/111121615): Need to fill out this hook */
-	/* Enable display backlight. */
-	gpio_set_level(GPIO_EDP_BKTLEN_OD, 0);
-}
-DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend,
-	     HOOK_PRIO_DEFAULT);
-
-/* Called on AP S3 -> S5 transition */
-static void baseboard_chipset_shutdown(void)
-{
-	/* TODD(b/111121615): Need to fill out this hook */
-}
-DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, baseboard_chipset_shutdown,
-	     HOOK_PRIO_DEFAULT);
-
-void board_hibernate(void)
-{
-	int timeout_ms = 20;
-	/*
-	 * Disable the TCPC power rail and the PP5000 rail before going into
-	 * hibernate. Note, these 2 rails are powered up as the default state in
-	 * gpio.inc.
-	 */
-	gpio_set_level(GPIO_EN_PP5000, 0);
-	/* Wait for PP5000 to drop before disabling PP3300_TCPC */
-	while (gpio_get_level(GPIO_PP5000_PG_OD) && timeout_ms > 0) {
-		msleep(1);
-		timeout_ms--;
-	}
-	if (!timeout_ms)
-		CPRINTS("PP5000_PG didn't go low after 20 msec");
-	gpio_set_level(GPIO_EN_PP3300_TCPC, 0);
-}
-/******************************************************************************/
-/* USB-C TPCP Configuration */
-const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ITE_0] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it83xx_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-
-	[USB_PD_PORT_ITE_1] = {
-		.bus_type = EC_BUS_TYPE_EMBEDDED,
-		/* TCPC is embedded within EC so no i2c config needed */
-		.drv = &it83xx_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-
-	[USB_PD_PORT_TUSB422_2] = {
-		.bus_type = EC_BUS_TYPE_I2C,
-		.i2c_info = {
-			.port = I2C_PORT_USBC1C2,
-			.addr_flags = TUSB422_I2C_ADDR_FLAGS,
-		},
-		.drv = &tusb422_tcpm_drv,
-		/* Alert is active-low, push-pull */
-		.flags = 0,
-	},
-};
-
-/******************************************************************************/
-/* USB-C PPC Configuration */
-struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ITE_0] = {
-		.i2c_port = I2C_PORT_USBC0,
-		.i2c_addr_flags = SN5S330_ADDR0_FLAGS,
-		.drv = &sn5s330_drv
-	},
-
-	[USB_PD_PORT_ITE_1] = {
-		.i2c_port = I2C_PORT_USBC1C2,
-		.i2c_addr_flags = SYV682X_ADDR0_FLAGS,
-		.drv = &syv682x_drv
-	},
-
-	[USB_PD_PORT_TUSB422_2] = {
-		.i2c_port = I2C_PORT_USBC1C2,
-		.i2c_addr_flags = NX20P3481_ADDR2_FLAGS,
-		.drv = &nx20p348x_drv,
-	},
-};
-unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
-
-const struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	[USB_PD_PORT_ITE_0] = {
-		.usb_port = USB_PD_PORT_ITE_0,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-
-	[USB_PD_PORT_ITE_1] = {
-		.usb_port = USB_PD_PORT_ITE_1,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-
-	[USB_PD_PORT_TUSB422_2] = {
-		.usb_port = USB_PD_PORT_TUSB422_2,
-		.driver = &virtual_usb_mux_driver,
-		.hpd_update = &virtual_hpd_update,
-	},
-};
-
-/******************************************************************************/
-/* BC 1.2 chip Configuration */
-const struct max14637_config_t max14637_config[CONFIG_USB_PD_PORT_MAX_COUNT] = {
-	{
-		.chip_enable_pin = GPIO_USB_C0_BC12_VBUS_ON_ODL,
-		.chg_det_pin = GPIO_USB_C0_BC12_CHG_MAX,
-		.flags = MAX14637_FLAGS_ENABLE_ACTIVE_LOW,
-	},
-	{
-		.chip_enable_pin = GPIO_USB_C1_BC12_VBUS_ON_ODL,
-		.chg_det_pin = GPIO_USB_C1_BC12_CHG_MAX,
-		.flags = MAX14637_FLAGS_ENABLE_ACTIVE_LOW,
-	},
-	{
-		.chip_enable_pin = GPIO_USB_C2_BC12_VBUS_ON_ODL,
-		.chg_det_pin = GPIO_USB_C2_BC12_CHG_MAX,
-		.flags = MAX14637_FLAGS_ENABLE_ACTIVE_LOW,
-	},
-};
-
-/* Power Delivery and charging functions */
-
-void baseboard_tcpc_init(void)
-{
-	/* Enable PPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C0_TCPPC_INT_L);
-	gpio_enable_interrupt(GPIO_USB_C2_TCPPC_INT_ODL);
-
-	/* Enable TCPC interrupts. */
-	gpio_enable_interrupt(GPIO_USB_C2_TCPC_INT_ODL);
-
-}
-DECLARE_HOOK(HOOK_INIT, baseboard_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
-
-uint16_t tcpc_get_alert_status(void)
-{
-	uint16_t status = 0;
-	/*
-	 * Since C0/C1 TCPC are embedded within EC, we don't need the PDCMD
-	 * tasks.The (embedded) TCPC status since chip driver code will
-	 * handles its own interrupts and forward the correct events to
-	 * the PD_C0 task. See it83xx/intc.c
-	 */
-
-	if (!gpio_get_level(GPIO_USB_C2_TCPC_INT_ODL))
-		status = PD_STATUS_TCPC_ALERT_2;
-
-	return status;
-}
-
-/**
- * Reset all system PD/TCPC MCUs -- currently only called from
- * handle_pending_reboot() in common/power.c just before hard
- * resetting the system. This logic is likely not needed as the
- * PP3300_A rail should be dropped on EC reset.
- */
-void board_reset_pd_mcu(void)
-{
-	/*
-	 * C0 & C1: The internal TCPC on ITE EC does not have a reset signal,
-	 * but it will get reset when the EC gets reset.
-	 */
-}
-void board_pd_vconn_ctrl(int port, enum usbpd_cc_pin cc_pin, int enabled)
-{
-	/*
-	 * We ignore the cc_pin because the polarity should already be set
-	 * correctly in the PPC driver via the pd state machine.
-	 */
-	if (ppc_set_vconn(port, enabled) != EC_SUCCESS)
-		cprints(CC_USBPD, "C%d: Failed %sabling vconn",
-			port, enabled ? "en" : "dis");
-}
-
-int board_set_active_charge_port(int port)
-{
-	int is_valid_port = (port >= 0 &&
-			    port < CONFIG_USB_PD_PORT_MAX_COUNT);
-	int i;
-
-	if (!is_valid_port && port != CHARGE_PORT_NONE)
-		return EC_ERROR_INVAL;
-
-	if (port == CHARGE_PORT_NONE) {
-		CPRINTSUSB("Disabling all charger ports");
-
-		/* Disable all ports. */
-		for (i = 0; i < ppc_cnt; i++) {
-			/*
-			 * Do not return early if one fails otherwise we can
-			 * get into a boot loop assertion failure.
-			 */
-			if (ppc_vbus_sink_enable(i, 0))
-				CPRINTSUSB("Disabling C%d as sink failed.", i);
-		}
-
-		return EC_SUCCESS;
-	}
-
-	/* Check if the port is sourcing VBUS. */
-	if (ppc_is_sourcing_vbus(port)) {
-		CPRINTFUSB("Skip enable C%d", port);
-		return EC_ERROR_INVAL;
-	}
-
-	CPRINTSUSB("New charge port: C%d", port);
-
-	/*
-	 * Turn off the other ports' sink path FETs, before enabling the
-	 * requested charge port.
-	 */
-	for (i = 0; i < ppc_cnt; i++) {
-		if (i == port)
-			continue;
-
-		if (ppc_vbus_sink_enable(i, 0))
-			CPRINTSUSB("C%d: sink path disable failed.", i);
-	}
-
-	/* Enable requested charge port. */
-	if (ppc_vbus_sink_enable(port, 1)) {
-		CPRINTSUSB("C%d: sink path enable failed.", port);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	return EC_SUCCESS;
-}
-
-void board_set_charge_limit(int port, int supplier, int charge_ma,
-			    int max_ma, int charge_mv)
-{
-	charge_set_input_current_limit(MAX(charge_ma,
-					   CONFIG_CHARGER_INPUT_CURRENT),
-				       charge_mv);
-}
diff --git a/baseboard/dragonegg/baseboard.h b/baseboard/dragonegg/baseboard.h
deleted file mode 100644
index 47edb8f314..0000000000
--- a/baseboard/dragonegg/baseboard.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* DragonEgg board configuration */
-
-#ifndef __CROS_EC_BASEBOARD_H
-#define __CROS_EC_BASEBOARD_H
-
-/* EC console commands  */
-#define CONFIG_CMD_BATT_MFG_ACCESS
-
-#define CONFIG_CHIPSET_ICELAKE
-#define CONFIG_CHIPSET_RESET_HOOK
-#define CONFIG_EXTPOWER_GPIO
-#define CONFIG_HOSTCMD_ESPI
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S3
-#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4
-#define CONFIG_MKBP_EVENT
-#define CONFIG_MKBP_USE_HOST_EVENT
-#define CONFIG_POWER_BUTTON
-#define CONFIG_POWER_BUTTON_X86
-#define CONFIG_POWER_PP5000_CONTROL
-/* TODO(b/111155507): Don't enable SOiX for now */
-/* #define CONFIG_POWER_S0IX */
-/* #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
-
-/* EC Defines */
-#define CONFIG_ADC
-#define CONFIG_PWM
-#define CONFIG_VBOOT_HASH
-#define CONFIG_VSTORE
-#define CONFIG_VSTORE_SLOT_COUNT 1
-
-/* CBI */
-/*
- * TODO (b/117174246): When EEPROMs are programmed, can use EEPROM for board
- * version. But for P0/P1 boards rely on GPIO signals.
- */
-/* #define CONFIG_BOARD_VERSION_CBI */
-#define CONFIG_CBI_EEPROM
-#define CONFIG_CRC8
-
-/* Common Keyboard Defines */
-#define CONFIG_CMD_KEYBOARD
-
-#define CONFIG_KEYBOARD_PROTOCOL_8042
-#define CONFIG_KEYBOARD_COL2_INVERTED
-#define CONFIG_KEYBOARD_PWRBTN_ASSERTS_KSI2
-
-/* Common charger defines */
-#define CONFIG_CHARGE_MANAGER
-#define CONFIG_CHARGE_RAMP_HW
-#define CONFIG_CHARGER
-#define CONFIG_CHARGER_BQ25710
-#define CONFIG_CHARGER_DISCHARGE_ON_AC
-#define CONFIG_CHARGER_INPUT_CURRENT 512 /* Allow low-current USB charging */
-#define CONFIG_CHARGER_SENSE_RESISTOR 10
-#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
-
-/* Common battery defines */
-#define CONFIG_BATTERY_CUT_OFF
-#define CONFIG_BATTERY_DEVICE_CHEMISTRY  "LION"
-#define CONFIG_BATTERY_FUEL_GAUGE
-#define CONFIG_BATTERY_HW_PRESENT_CUSTOM
-#define CONFIG_BATTERY_PRESENT_CUSTOM
-#define CONFIG_BATTERY_REVIVE_DISCONNECT
-#define CONFIG_BATTERY_SMART
-
-/* BC 1.2 Detection */
-#define CONFIG_BC12_DETECT_MAX14637
-#define CONFIG_USB_CHARGER
-
-/* USB Type C and USB PD defines */
-#undef CONFIG_USB_PD_TCPC_LOW_POWER
-#undef CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP	/* C0 & C1 TCPC: ITE EC */
-#define CONFIG_USB_PD_TCPM_TUSB422	/* C1 TCPC: TUSB422 */
-#define CONFIG_USB_POWER_DELIVERY
-#define CONFIG_USB_PD_TCPMV1
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
-
-/*
- * TODO (b/111281797): DragonEgg has 3 ports. Only adding support for the port
- * on the MLB for now. In addition, this config option will likely move to
- * board.h as it likely board dependent and not same across all follower boards.
- */
-#define CONFIG_USB_PD_PORT_MAX_COUNT 3
-#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
-#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_LOGGING
-#define CONFIG_USB_PD_ALT_MODE
-#define CONFIG_USB_PD_ALT_MODE_DFP
-#define CONFIG_USB_PD_DISCHARGE_PPC
-#define CONFIG_USB_PD_TRY_SRC
-#define CONFIG_USB_PD_VBUS_DETECT_PPC
-#define CONFIG_USB_PD_TCPM_TCPCI
-#define CONFIG_USB_MUX_VIRTUAL
-#define CONFIG_USBC_PPC_SN5S330		/* C0 PPC */
-#define CONFIG_USBC_PPC_SYV682X		/* C1 PPC */
-#define CONFIG_USBC_PPC_NX20P3481		/* C2 PPC */
-#define CONFIG_USBC_PPC_VCONN
-#define CONFIG_USBC_SS_MUX
-#define CONFIG_USBC_VCONN
-#define CONFIG_USBC_VCONN_SWAP
-
-#define CONFIG_HOSTCMD_PD_CONTROL
-#define CONFIG_CMD_PPC_DUMP
-
-/* TODO(b/111281797): Use correct PD delay values */
-#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000	/* us */
-#define PD_POWER_SUPPLY_TURN_OFF_DELAY	250000	/* us */
-
-/* TODO(b/111281797): Use correct PD power values */
-#define PD_OPERATING_POWER_MW	15000
-#define PD_MAX_POWER_MW		45000
-#define PD_MAX_CURRENT_MA	3000
-#define PD_MAX_VOLTAGE_MV	20000
-
-/* IT83XX config */
-#define CONFIG_IT83XX_VCC_1P8V
-/* I2C Bus Configuration */
-#define CONFIG_I2C
-#define CONFIG_I2C_CONTROLLER
-#define I2C_PORT_BATTERY	IT83XX_I2C_CH_F	/* Shared bus */
-#define I2C_PORT_CHARGER	IT83XX_I2C_CH_F	/* Shared bus */
-#define I2C_PORT_SENSOR		IT83XX_I2C_CH_B
-#define I2C_PORT_USBC0		IT83XX_I2C_CH_E
-#define I2C_PORT_USBC1C2	IT83XX_I2C_CH_C
-#define I2C_PORT_EEPROM		IT83XX_I2C_CH_A
-#define I2C_ADDR_EEPROM_FLAGS	0x50
-
-#ifndef __ASSEMBLER__
-
-/* Forward declare common (within DragonEgg) board-specific functions */
-void board_reset_pd_mcu(void);
-
-#endif /* !__ASSEMBLER__ */
-
-#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/dragonegg/battery.c b/baseboard/dragonegg/battery.c
deleted file mode 100644
index 0c4ec32903..0000000000
--- a/baseboard/dragonegg/battery.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Battery pack vendor provided charging profile
- */
-
-#include "battery.h"
-#include "battery_fuel_gauge.h"
-#include "battery_smart.h"
-#include "gpio.h"
-#include "system.h"
-
-static enum battery_present batt_pres_prev = BP_NOT_SURE;
-
-enum battery_present battery_hw_present(void)
-{
-	enum battery_present bp;
-	/* The GPIO is low when the battery is physically present */
-	/*
-	 * TODO(b/111704193): The signal GPIO_EC_BATT_PRES_ODL has an issue
-	 * where it's floating (?) at ~2V when it should be low when the battery
-	 * is connected. The signal will read correctly following a cold reset
-	 * and the battery is connected, but following a warm reboot, it reads
-	 * high. In order to allow charging to work, replacing this with the a
-	 * check that the Operation Status register can be read. Once the HW
-	 * issue is resolved then change this back to checking the physical
-	 * presence pin.
-	 *
-	 */
-
-	if (system_get_board_version() == 0)
-		/* P0 boards can't use gpio signal */
-		bp = (battery_get_disconnect_state() ==
-		      BATTERY_DISCONNECT_ERROR) ? BP_NO : BP_YES;
-	else
-		/* P1 boards can read presence from gpio signal */
-		bp = gpio_get_level(GPIO_EC_BATT_PRES_ODL) ? BP_NO : BP_YES;
-
-	return bp;
-}
-
-static int battery_init(void)
-{
-	int batt_status;
-
-	return battery_status(&batt_status) ? 0 :
-		!!(batt_status & STATUS_INITIALIZED);
-}
-
-/*
- * Physical detection of battery.
- */
-static enum battery_present battery_check_present_status(void)
-{
-	enum battery_present batt_pres;
-
-	/* Get the physical hardware status */
-	batt_pres = battery_hw_present();
-
-	/*
-	 * If the battery is not physically connected, then no need to perform
-	 * any more checks.
-	 */
-	if (batt_pres != BP_YES)
-		return batt_pres;
-
-	/*
-	 * If the battery is present now and was present last time we checked,
-	 * return early.
-	 */
-	if (batt_pres == batt_pres_prev)
-		return batt_pres;
-
-	/*
-	 * Ensure that battery is:
-	 * 1. Not in cutoff
-	 * 2. Initialized
-	 */
-	if (battery_is_cut_off() != BATTERY_CUTOFF_STATE_NORMAL ||
-	    battery_init() == 0) {
-		batt_pres = BP_NO;
-	}
-
-	return batt_pres;
-}
-
-enum battery_present battery_is_present(void)
-{
-	batt_pres_prev = battery_check_present_status();
-	return batt_pres_prev;
-}
diff --git a/baseboard/dragonegg/build.mk b/baseboard/dragonegg/build.mk
deleted file mode 100644
index 7f3c8a3669..0000000000
--- a/baseboard/dragonegg/build.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-# -*- makefile -*-
-# Copyright 2018 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# DragonEgg baseboard specific files build
-#
-
-baseboard-y=baseboard.o
-baseboard-$(CONFIG_BATTERY_SMART)+=battery.o
-baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
diff --git a/baseboard/dragonegg/usb_pd_policy.c b/baseboard/dragonegg/usb_pd_policy.c
deleted file mode 100644
index 85eeecdcf9..0000000000
--- a/baseboard/dragonegg/usb_pd_policy.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Shared USB-C policy for DragonEgg boards */
-
-#include "charge_manager.h"
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "ec_commands.h"
-#include "gpio.h"
-#include "system.h"
-#include "tcpm/tcpci.h"
-#include "tcpm/tcpm.h"
-#include "usb_mux.h"
-#include "usb_pd.h"
-#include "usbc_ppc.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
-#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
-
-int pd_check_vconn_swap(int port)
-{
-	/* Only allow vconn swap if pp5000_A rail is enabled */
-	return gpio_get_level(GPIO_EN_PP5000);
-}
-
-__override void pd_execute_data_swap(int port,
-				     enum pd_data_role data_role)
-{
-	/* On DragonEgg, only the first port can act as OTG */
-	if (port == 0)
-		gpio_set_level(GPIO_CHG_VAP_OTG_EN, (data_role == PD_ROLE_UFP));
-}
-
-void pd_power_supply_reset(int port)
-{
-	int prev_en;
-
-	prev_en = ppc_is_sourcing_vbus(port);
-
-	/* Disable VBUS. */
-	ppc_vbus_source_enable(port, 0);
-
-	/* Enable discharge if we were previously sourcing 5V */
-	if (prev_en)
-		pd_set_vbus_discharge(port, 1);
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Give back the current quota we are no longer using */
-	charge_manager_source_port(port, 0);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-}
-
-int pd_set_power_supply_ready(int port)
-{
-	int rv;
-
-	/* Disable charging. */
-	rv = ppc_vbus_sink_enable(port, 0);
-	if (rv)
-		return rv;
-
-	pd_set_vbus_discharge(port, 0);
-
-	/* Provide Vbus. */
-	rv = ppc_vbus_source_enable(port, 1);
-	if (rv)
-		return rv;
-
-#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
-	/* Ensure we advertise the proper available current quota */
-	charge_manager_source_port(port, 1);
-#endif /* defined(CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT) */
-
-	/* Notify host of power info change. */
-	pd_send_host_event(PD_EVENT_POWER_CHANGE);
-
-	return EC_SUCCESS;
-}
-
-#ifdef CONFIG_USB_PD_VBUS_DETECT_PPC
-int pd_snk_is_vbus_provided(int port)
-{
-	/*
-	 * TODO(b/112661747): Until per port VBUS detection methods are
-	 * supported, DragonEgg needs to have CONFIG_USB_PD_VBUS_DETECT_PPC
-	 * defined, but the nx20p3481 PPC on port 2 does not support VBUS
-	 * detection. In the meantime, check specifically for port 2, and rely
-	 * on the TUSB422 TCPC for VBUS status. Note that the tcpm method can't
-	 * be called directly here as it's not supported unless
-	 * CONFIG_USB_PD_VBUS_DETECT_TCPC is defined.
-	 */
-	int reg;
-
-	if (port == 2) {
-		if (tcpc_read(port, TCPC_REG_POWER_STATUS, &reg))
-			return 0;
-		return reg & TCPC_REG_POWER_STATUS_VBUS_PRES ? 1 : 0;
-	}
-	return ppc_is_vbus_present(port);
-}
-#endif
-
-int board_vbus_source_enabled(int port)
-{
-	return ppc_is_sourcing_vbus(port);
-}