diff options
author | Aseda Aboagye <aaboagye@google.com> | 2020-02-15 13:34:45 -0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-02-21 10:30:11 +0000 |
commit | bbbd07dbe113d0c65c15c6ef997bb55fa82575e6 (patch) | |
tree | 30c4272467b393907dd02d60d4e640332193b1a3 /baseboard | |
parent | f5e6d1888ac11686305c55fcc54f74ef131c6792 (diff) | |
download | chrome-ec-bbbd07dbe113d0c65c15c6ef997bb55fa82575e6.tar.gz |
dedede: Set pullup on PG_PP1050_ST_OD only after RSMRST
Per recommendation from the SoC vendor, we should only enable the pull
up on PG_PP1050_ST_OD once RSMRST has been de-asserted. Otherwise, the
pull up can inidicate a false power good.
BUG=b:148688874
BRANCH=None
TEST=Build and flash waddledoo, verify that PG_PP1050_ST_OD is actually
valid.
Change-Id: Icdd8ec08fc84954730ae2d80fed86af4f07f01ba
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2058694
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Diffstat (limited to 'baseboard')
-rw-r--r-- | baseboard/dedede/baseboard.c | 17 | ||||
-rw-r--r-- | baseboard/dedede/baseboard.h | 1 |
2 files changed, 18 insertions, 0 deletions
diff --git a/baseboard/dedede/baseboard.c b/baseboard/dedede/baseboard.c index fcf8f275fc..9f6a37d3d1 100644 --- a/baseboard/dedede/baseboard.c +++ b/baseboard/dedede/baseboard.c @@ -6,6 +6,7 @@ /* Dedede family-specific configuration */ #include "adc.h" +#include "board_config.h" #include "chipset.h" #include "common.h" #include "gpio.h" @@ -21,6 +22,22 @@ const enum gpio_signal hibernate_wake_pins[] = {}; const int hibernate_wake_pins_used; +void board_after_rsmrst(int rsmrst) +{ + /* + * b:148688874: If RSMRST# is de-asserted, enable the pull-up on + * PG_PP1050_ST_OD. It won't be enabled prior to this signal going high + * because the load switch for PP1050_ST cannot pull the PG low. Once + * it's asserted, disable the pull up so we don't inidicate that the + * power is good before the rail is actually ready. + */ + int flags = rsmrst ? GPIO_PULL_UP : 0; + + flags |= GPIO_INT_BOTH; + + gpio_set_flags(GPIO_PG_PP1050_ST_OD, flags); +} + uint32_t pp3300_a_pgood; __override int intel_x86_get_pg_ec_dsw_pwrok(void) { diff --git a/baseboard/dedede/baseboard.h b/baseboard/dedede/baseboard.h index df6903193c..1494bdc79f 100644 --- a/baseboard/dedede/baseboard.h +++ b/baseboard/dedede/baseboard.h @@ -127,6 +127,7 @@ #define CONFIG_PWM /* SoC */ +#define CONFIG_BOARD_HAS_AFTER_RSMRST #define CONFIG_BOARD_HAS_RTC_RESET #define CONFIG_CHIPSET_JASPERLAKE #define CONFIG_POWER_BUTTON |