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| author | Tinghan Shen <tinghan.shen@mediatek.com> | 2022-05-11 19:43:47 +0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-05-13 06:15:54 +0000 |
| commit | fd0e4ff15f3762dbcae34023ca57044eaf0087a5 (patch) | |
| tree | 6128ba35678e3d79252c42b7ec587a9382143222 /baseboard | |
| parent | 7d03da76a7360483a00c499532cac0c3375067c3 (diff) | |
| download | chrome-ec-fd0e4ff15f3762dbcae34023ca57044eaf0087a5.tar.gz | |
chip/mt_scp: fix 8192 boot fail
8192 doesn't support saving panic information on DRAM.
It should not define CONFIG_PANIC_DATA_BASE.
BRANCH=none
BUG=b:184793035
TEST=make BOARD=asurada_scp and boot ok
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Change-Id: I6492f986398ba27261a076b9647ddc0660c4d3f4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3640989
Reviewed-by: Wei-Shun Chang <weishunc@chromium.org>
Commit-Queue: Wei-Shun Chang <weishunc@chromium.org>
Diffstat (limited to 'baseboard')
| -rw-r--r-- | baseboard/mtscp-rv32i/baseboard.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/baseboard/mtscp-rv32i/baseboard.h b/baseboard/mtscp-rv32i/baseboard.h index d7694cd1c7..3af9fe1af9 100644 --- a/baseboard/mtscp-rv32i/baseboard.h +++ b/baseboard/mtscp-rv32i/baseboard.h @@ -60,7 +60,10 @@ #define CONFIG_PANIC_DRAM_SIZE 0x00001000 /* 4K */ #define CONFIG_PANIC_BASE_OFFSET 0x100 /* reserved for jump data */ + +#ifdef CHIP_VARIANT_MT8195 #define CONFIG_PANIC_DATA_BASE (CONFIG_PANIC_DRAM_BASE + CONFIG_PANIC_BASE_OFFSET) +#endif /* MPU settings */ #define NR_MPU_ENTRIES 16 |