Revert "intelrvp: Remove TGLRVP & JSLRVP boards and MECC0.9"

This reverts commit eaa6e6a4939437075f13d9f91beda09fd150b1cc.

Reason for revert: b/211053714 - build failures

Original change's description:
> intelrvp: Remove TGLRVP & JSLRVP boards and MECC0.9
>
> As support for TGLRVP & JSLRVP has reached end of life remove these
> boards and also support for MECC0.9 that applies only to TGLRVP &
> JSLRVP.
>
> BUG=none
> BRANCH=none
> TEST=make buildall -j
>
> Cq-Include-Trybots: luci.chromeos.cq:cq-orchestrator
> Change-Id: Ic2acb2e87c6db8395a9e8caeaedf130b9dbc3891
> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3238255
> Reviewed-by: Poornima Tom <poornima.tom@intel.com>
> Reviewed-by: Keith Short <keithshort@chromium.org>
> Commit-Queue: Keith Short <keithshort@chromium.org>

Bug: b:211053714
Change-Id: I8102fbdc17859f114a80f87224d165e92ed92729
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3344725
Reviewed-by: Seewai Fu <seewaifu@google.com>
Commit-Queue: Brian Norris <briannorris@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>

6 files changed, 237 insertions, 5 deletions

diff --git a/baseboard/intelrvp/README.md b/baseboard/intelrvp/README.md
index 3405633132..39286e130d 100644
--- a/baseboard/intelrvp/README.md
+++ b/baseboard/intelrvp/README.md
@@ -10,13 +10,25 @@ baseboard code is applicable to Icelake and its successors only.
 Following hardware features are supported on MECC header by RVP and can be
 validated by software by MECC.
 
+## MECC version 0.9 features
+
+1.  Power to MECC is provided by RVP (battery + DC Jack + Type C)
+2.  Power control pins for Intel SOC are added
+3.  Servo V2 header need to be added by MECC
+4.  Google H1 chip need to be added by MECC (optional for EC vendors)
+5.  2 Type-C port support (SRC/SNK/BC1.2/MUX/Rerimer)
+6.  6 Temperature sensors
+7.  4 ADC
+8.  4 I2C Channels
+9.  1 Fan control
+
 ## MECC version 1.0 features
 
 1.  Power to MECC is provided by RVP (battery + DC Jack + Type C)
 2.  Power control pins for Intel SOC are added
 3.  Servo V2 header need to be added by MECC
 4.  Google H1 chip need to be added by MECC (optional for EC vendors)
-5.  4 Type-C port support (SRC/SNK/MUX/Rerimer) as Add In Card (AIC) on
+5.  4 Type-C port support (SRC/SNK/BC1.2/MUX/Rerimer) as Add In Card (AIC) on
     RVP
 6.  Optional 2 Type-C port routed to MECC for integrated TCPC support
 7.  6 I2C Channels
diff --git a/baseboard/intelrvp/baseboard.h b/baseboard/intelrvp/baseboard.h
index 0ab8ea2bc6..8f7d22350e 100644
--- a/baseboard/intelrvp/baseboard.h
+++ b/baseboard/intelrvp/baseboard.h
@@ -86,15 +86,25 @@
 
 /* USB-A config */
 
+/* BC1.2 config */
+#ifdef HAS_TASK_USB_CHG_P0
+	#define CONFIG_CHARGE_RAMP_HW
+#endif
+
 /* Enable USB-PD REV 3.0 */
 #define CONFIG_USB_PD_REV30
 #define CONFIG_USB_PID 0x8086
 
 /* USB PD config */
-#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_PD_DECODE_SOP
-#define CONFIG_USB_PD_TCPMV2
-#define CONFIG_USB_PD_TCPM_MUX
+#if defined(BOARD_TGLRVPU_ITE_TCPMV1) || defined(BOARD_TGLRVPY_ITE_TCPMV1)
+	#define CONFIG_USB_PD_TCPMV1
+	#define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0
+#else
+	#define CONFIG_USB_DRP_ACC_TRYSRC
+	#define CONFIG_USB_PD_DECODE_SOP
+	#define CONFIG_USB_PD_TCPMV2
+	#define CONFIG_USB_PD_TCPM_MUX
+#endif
 #define CONFIG_USB_PD_ALT_MODE
 #define CONFIG_USB_PD_ALT_MODE_DFP
 #define CONFIG_USB_PD_DUAL_ROLE
diff --git a/baseboard/intelrvp/bc12.c b/baseboard/intelrvp/bc12.c
new file mode 100644
index 0000000000..9f212fba4e
--- /dev/null
+++ b/baseboard/intelrvp/bc12.c
@@ -0,0 +1,28 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel BASEBOARD-RVP BC1.2 specific configuration */
+
+#include "common.h"
+#include "max14637.h"
+
+/* BC1.2 chip Configuration */
+#ifdef CONFIG_BC12_DETECT_MAX14637
+const struct max14637_config_t max14637_config[] = {
+	[TYPE_C_PORT_0] = {
+		.chip_enable_pin = GPIO_USB_C0_BC12_VBUS_ON_ODL,
+		.chg_det_pin = GPIO_USB_C0_BC12_CHG_DET_L,
+		.flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW,
+	},
+#ifdef HAS_TASK_PD_C1
+	[TYPE_C_PORT_1] = {
+		.chip_enable_pin = GPIO_USB_C1_BC12_VBUS_ON_ODL,
+		.chg_det_pin = GPIO_USB_C1_BC12_CHG_DET_L,
+		.flags = MAX14637_FLAGS_CHG_DET_ACTIVE_LOW,
+	},
+#endif /* HAS_TASK_PD_C1 */
+};
+BUILD_ASSERT(ARRAY_SIZE(max14637_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
+#endif /* CONFIG_BC12_DETECT_MAX14637 */
diff --git a/baseboard/intelrvp/build.mk b/baseboard/intelrvp/build.mk
index 5679d327a0..6abf8bbe0c 100644
--- a/baseboard/intelrvp/build.mk
+++ b/baseboard/intelrvp/build.mk
@@ -12,6 +12,8 @@ baseboard-$(CONFIG_LED_COMMON)+=led.o led_states.o
 
 ifneq ($(CONFIG_USB_POWER_DELIVERY),)
 baseboard-$(CONFIG_USB_POWER_DELIVERY)+=chg_usb_pd.o
+baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_0_9)+=chg_usb_pd_mecc_0_9.o
+baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_0_9)+=usb_pd_policy_mecc_0_9.o
 baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_1_0)+=chg_usb_pd_mecc_1_0.o
 baseboard-$(CONFIG_INTEL_RVP_MECC_VERSION_1_0)+=usb_pd_policy_mecc_1_0.o
 endif
@@ -21,6 +23,9 @@ baseboard-$(VARIANT_INTELRVP_EC_IT8320)+=ite_ec.o
 baseboard-$(VARIANT_INTELRVP_EC_MCHP)+=mchp_ec.o
 baseboard-$(VARIANT_INTELRVP_EC_NPCX)+=npcx_ec.o
 
+#BC1.2 specific files
+baseboard-$(CONFIG_BC12_DETECT_MAX14637)+=bc12.o
+
 #Common board specific files
 ifneq ($(filter y,$(BOARD_ADLRVPP_ITE) $(BOARD_ADLRVPM_ITE) \
 		$(BOARD_ADLRVPP_MCHP1521) $(BOARD_ADLRVPP_NPCX) \
diff --git a/baseboard/intelrvp/chg_usb_pd_mecc_0_9.c b/baseboard/intelrvp/chg_usb_pd_mecc_0_9.c
new file mode 100644
index 0000000000..fa9f1e147f
--- /dev/null
+++ b/baseboard/intelrvp/chg_usb_pd_mecc_0_9.c
@@ -0,0 +1,120 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel-RVP family-specific configuration */
+
+#include "console.h"
+#include "hooks.h"
+#include "tcpm/tcpci.h"
+#include "system.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+
+/* Reset PD MCU */
+void board_reset_pd_mcu(void)
+{
+	/* Add code if TCPC chips need a reset */
+}
+
+int board_vbus_source_enabled(int port)
+{
+	int src_en = 0;
+
+	/* Only Type-C ports can source VBUS */
+	if (is_typec_port(port)) {
+		src_en = gpio_get_level(tcpc_gpios[port].src.pin);
+
+		src_en = tcpc_gpios[port].src.pin_pol ? src_en : !src_en;
+	}
+
+	return src_en;
+}
+
+void board_set_vbus_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	int ilim_en;
+
+	/* Only Type-C ports can source VBUS */
+	if (is_typec_port(port)) {
+		/* Enable SRC ILIM if rp is MAX single source current */
+		ilim_en = (rp ==  TYPEC_RP_3A0 &&
+			board_vbus_source_enabled(port));
+
+		gpio_set_level(tcpc_gpios[port].src_ilim.pin,
+				tcpc_gpios[port].src_ilim.pin_pol ?
+				ilim_en : !ilim_en);
+	}
+}
+
+void board_charging_enable(int port, int enable)
+{
+	gpio_set_level(tcpc_gpios[port].snk.pin,
+		tcpc_gpios[port].snk.pin_pol ? enable : !enable);
+
+}
+
+void board_vbus_enable(int port, int enable)
+{
+	gpio_set_level(tcpc_gpios[port].src.pin,
+		tcpc_gpios[port].src.pin_pol ? enable : !enable);
+}
+
+int pd_snk_is_vbus_provided(int port)
+{
+	int vbus_intr;
+
+#if CONFIG_DEDICATED_CHARGE_PORT_COUNT > 0
+	if (port == DEDICATED_CHARGE_PORT)
+		return 1;
+#endif
+
+	vbus_intr = gpio_get_level(tcpc_gpios[port].vbus.pin);
+
+	return tcpc_gpios[port].vbus.pin_pol ? vbus_intr : !vbus_intr;
+}
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++) {
+		if (tcpc_gpios[i].vbus.pin == signal) {
+			schedule_deferred_pd_interrupt(i);
+			break;
+		}
+	}
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+	int i;
+
+	/* Check which port has the ALERT line set */
+	for (i = 0; i < CHARGE_PORT_COUNT; i++) {
+		/* No alerts for embdeded TCPC */
+		if (tcpc_config[i].bus_type == EC_BUS_TYPE_EMBEDDED)
+			continue;
+
+		/* Add TCPC alerts if present */
+	}
+
+	return status;
+}
+
+void board_tcpc_init(void)
+{
+	int i;
+
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_late())
+		board_reset_pd_mcu();
+
+	/* Enable TCPCx interrupt */
+	for (i = 0; i < CONFIG_USB_PD_PORT_MAX_COUNT; i++)
+		gpio_enable_interrupt(tcpc_gpios[i].vbus.pin);
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
diff --git a/baseboard/intelrvp/usb_pd_policy_mecc_0_9.c b/baseboard/intelrvp/usb_pd_policy_mecc_0_9.c
new file mode 100644
index 0000000000..6d173fd032
--- /dev/null
+++ b/baseboard/intelrvp/usb_pd_policy_mecc_0_9.c
@@ -0,0 +1,57 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "charge_manager.h"
+#include "console.h"
+#include "gpio.h"
+#include "system.h"
+#include "usb_mux.h"
+
+#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
+#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
+
+int pd_set_power_supply_ready(int port)
+{
+	/* Disable charging */
+	board_charging_enable(port, 0);
+
+	/* Provide VBUS */
+	board_vbus_enable(port, 1);
+
+#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
+	/* Ensure we advertise the proper available current quota */
+	charge_manager_source_port(port, 1);
+#endif
+
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS; /* we are ready */
+}
+
+void pd_power_supply_reset(int port)
+{
+	/* Disable VBUS */
+	board_vbus_enable(port, 0);
+
+#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
+	/* Give back the current quota we are no longer using */
+	charge_manager_source_port(port, 0);
+#endif
+
+	/* notify host of power info change */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_check_vconn_swap(int port)
+{
+	/* Only allow vconn swap if PP5000 rail is enabled */
+	return gpio_get_level(GPIO_EN_PP5000);
+}
+
+__override void typec_set_source_current_limit(int port, enum tcpc_rp_value rp)
+{
+	board_set_vbus_source_current_limit(port, rp);
+}