diff options
| author | Diana Z <dzigterman@chromium.org> | 2018-10-01 15:14:12 -0600 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-10-09 16:26:47 -0700 |
| commit | bb3f5b55257bf9ae1a0c695e4b8f870932137472 (patch) | |
| tree | 700d9cdfa331d6bfd0a11646c88c0b24338592a8 /baseboard | |
| parent | e79a7346922507aa12ecf6f488921f7d57ca7a95 (diff) | |
| download | chrome-ec-bb3f5b55257bf9ae1a0c695e4b8f870932137472.tar.gz | |
Octopus: add reset logic for C0 TCPC
This change adds a call to the C0 TCPC reset for standalone TCPC boards
which have that pin hooked up in hardware, and adds the GPIO as
unimplemented for boards which do not have this yet.
BRANCH=None
BUG=b:112756630
TEST=Added a log print and rebooted EC on bobba to verify TCPC C0 reset,
then verified that charging on C0 worked. Also imaged yorp proto 2 and
rebooted, verifying C0 reset was not attempted.
Change-Id: I615861f0d9ce9b5a89692e3982ed2e19c7e0b237
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1257647
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'baseboard')
| -rw-r--r-- | baseboard/octopus/variant_usbc_standalone_tcpcs.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/baseboard/octopus/variant_usbc_standalone_tcpcs.c b/baseboard/octopus/variant_usbc_standalone_tcpcs.c index 2068231519..b4affc197c 100644 --- a/baseboard/octopus/variant_usbc_standalone_tcpcs.c +++ b/baseboard/octopus/variant_usbc_standalone_tcpcs.c @@ -124,7 +124,23 @@ uint16_t tcpc_get_alert_status(void) */ void board_reset_pd_mcu(void) { - /* C0: ANX7447 does not have a reset pin. */ + /* + * C0: Assert reset to TCPC0 (ANX7447) for required delay (1ms) only if + * we have a battery + * + * Note: The TEST_R pin is not hooked up to a GPIO on all boards, so + * verify the name exists before setting it. After the name is + * introduced for later board firmware, this pin will still be wired + * to USB2_OTG_ID on the proto boards, which should be set to open + * drain so it can't be driven high. + */ + if (gpio_is_implemented(GPIO_USB_C0_PD_RST) && + battery_is_present() == BP_YES) { + gpio_set_level(GPIO_USB_C0_PD_RST, 1); + msleep(ANX74XX_RESET_HOLD_MS); + gpio_set_level(GPIO_USB_C0_PD_RST, 0); + msleep(ANX74XX_RESET_FINISH_MS); + } /* * C1: Assert reset to TCPC1 (PS8751) for required delay (1ms) only if |