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| author | Poornima Tom <poornima.tom@intel.com> | 2020-11-27 19:13:32 +0530 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-12-03 06:57:49 +0000 |
| commit | 414b245e6653dfe062c05d8b0f23620fdd65fdae (patch) | |
| tree | e8eabbc1a4cd0c6d438244b9fa05eac2f1f370de /board/adlrvpp_ite/board.h | |
| parent | 65feeb47e355aec8b7c971964811a8aac8e02124 (diff) | |
| download | chrome-ec-414b245e6653dfe062c05d8b0f23620fdd65fdae.tar.gz | |
ADLRVP: Remove PP5000 rail config
Both 3.3A & 5VA rail come up or go down together by EC_DS4 signal
hence removed PP5000 rail config.
BRANCH=None
BUG=b:169551130
TEST=make build all; Tested on ADLRVP
Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Change-Id: I7c3a66b53ada616071998d111bf822a5b7fbcc81
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563425
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Sooraj Govindan <sooraj.govindan@intel.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Tested-by: Sooraj Govindan <sooraj.govindan@intel.com>
Diffstat (limited to 'board/adlrvpp_ite/board.h')
| -rw-r--r-- | board/adlrvpp_ite/board.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/board/adlrvpp_ite/board.h b/board/adlrvpp_ite/board.h index 96fa4324de..aae55b0b7c 100644 --- a/board/adlrvpp_ite/board.h +++ b/board/adlrvpp_ite/board.h @@ -21,7 +21,6 @@ /* Chipset */ #define CONFIG_CHIPSET_TIGERLAKE -#define CONFIG_POWER_PP5000_CONTROL /* * Macros for GPIO signals used in common code that don't match the |