adlrvpm: add Alderlake-M RVP support

Following features are enabled and verified.
   1. Power sequencing
   2. Host communication
   3. USB TYPE-C - TCPC over PD AIC
   4. H1 Close Case Debug
   5. LED
   6. Keyboard

BRANCH=None
BUG=b:169551130
TEST=Build, flash and boot the Alderlake RVP platform to OS
make BOARD=adlrvpm_ite -j;
sudo util/flash_ec --board=adlrvpm_ite --image=<path>

Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com>
Change-Id: I3ee12a0875cb6310c3b5767cab90f17f9646e02c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2584553
Tested-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>

3 files changed, 43 insertions, 1 deletions

diff --git a/board/adlrvpp_ite/board.c b/board/adlrvpp_ite/board.c
index 002b67d395..7c656f868e 100644
--- a/board/adlrvpp_ite/board.c
+++ b/board/adlrvpp_ite/board.c
@@ -89,6 +89,7 @@ const struct i2c_port_t i2c_ports[] = {
 		.scl = GPIO_USBC_TCPC_I2C_CLK_P2,
 		.sda = GPIO_USBC_TCPC_I2C_DATA_P2,
 	},
+#if defined(BOARD_ADLRVPP_ITE)
 	[I2C_CHAN_TYPEC_2] = {
 		.name = "typec_2",
 		.port = IT83XX_I2C_CH_E,
@@ -103,6 +104,7 @@ const struct i2c_port_t i2c_ports[] = {
 		.scl = GPIO_USBC_TCPC_I2C_CLK_P3,
 		.sda = GPIO_USBC_TCPC_I2C_DATA_P3,
 	},
+#endif
 };
 BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
@@ -119,6 +121,7 @@ const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = {
 		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P1,
 		.ppc_intr_handler = sn5s330_interrupt,
 	},
+#if defined(BOARD_ADLRVPP_ITE)
 	[TYPE_C_PORT_2] = {
 		.tcpc_alert = GPIO_USBC_TCPC_ALRT_P2,
 		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P2,
@@ -129,6 +132,7 @@ const struct tcpc_aic_gpio_config_t tcpc_aic_gpios[] = {
 		.ppc_alert = GPIO_USBC_TCPC_PPC_ALRT_P3,
 		.ppc_intr_handler = sn5s330_interrupt,
 	},
+#endif
 };
 BUILD_ASSERT(ARRAY_SIZE(tcpc_aic_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT);
 
@@ -147,6 +151,7 @@ const struct tcpc_config_t tcpc_config[] = {
 		},
 		.drv = &fusb302_tcpm_drv,
 	},
+#if defined(BOARD_ADLRVPP_ITE)
 	[TYPE_C_PORT_2] = {
 		.bus_type = EC_BUS_TYPE_I2C,
 		.i2c_info = {
@@ -163,6 +168,7 @@ const struct tcpc_config_t tcpc_config[] = {
 		},
 		.drv = &fusb302_tcpm_drv,
 	},
+#endif
 };
 BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
 
@@ -178,6 +184,7 @@ struct ppc_config_t ppc_chips[] = {
 		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
 		.drv = &sn5s330_drv
 	},
+#if defined(BOARD_ADLRVPP_ITE)
 	[TYPE_C_PORT_2] = {
 		.i2c_port = I2C_PORT_TYPEC_2,
 		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
@@ -188,6 +195,7 @@ struct ppc_config_t ppc_chips[] = {
 		.i2c_addr_flags = I2C_ADDR_SN5S330_TCPC_AIC_PPC,
 		.drv = &sn5s330_drv,
 	},
+#endif
 };
 BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == CONFIG_USB_PD_PORT_MAX_COUNT);
 unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
@@ -203,6 +211,7 @@ struct usb_mux usbc1_tcss_usb_mux = {
 	.driver = &virtual_usb_mux_driver,
 	.hpd_update = &virtual_hpd_update,
 };
+#if defined(BOARD_ADLRVPP_ITE)
 struct usb_mux usbc2_tcss_usb_mux = {
 	.usb_port = TYPE_C_PORT_2,
 	.driver = &virtual_usb_mux_driver,
@@ -213,6 +222,7 @@ struct usb_mux usbc3_tcss_usb_mux = {
 	.driver = &virtual_usb_mux_driver,
 	.hpd_update = &virtual_hpd_update,
 };
+#endif
 
 /* USB muxes Configuration */
 const struct usb_mux usb_muxes[] = {
@@ -230,6 +240,7 @@ const struct usb_mux usb_muxes[] = {
 		.i2c_port = I2C_PORT_TYPEC_1,
 		.i2c_addr_flags = I2C_PORT1_BB_RETIMER_ADDR,
 	},
+#if defined(BOARD_ADLRVPP_ITE)
 	[TYPE_C_PORT_2] = {
 		.usb_port = TYPE_C_PORT_2,
 		.next_mux = &usbc2_tcss_usb_mux,
@@ -244,6 +255,7 @@ const struct usb_mux usb_muxes[] = {
 		.i2c_port = I2C_PORT_TYPEC_3,
 		.i2c_addr_flags = I2C_PORT3_BB_RETIMER_ADDR,
 	},
+#endif
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
 
@@ -259,6 +271,7 @@ const struct pca9675_ioexpander pca9675_iox[] = {
 		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
 		.io_direction = TCPC_AIC_IOE_DIRECTION,
 	},
+#if defined(BOARD_ADLRVPP_ITE)
 	[TYPE_C_PORT_2] = {
 		.i2c_host_port = I2C_PORT_TYPEC_2,
 		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
@@ -269,6 +282,7 @@ const struct pca9675_ioexpander pca9675_iox[] = {
 		.i2c_addr_flags = I2C_ADDR_PCA9675_TCPC_AIC_IOEX,
 		.io_direction = TCPC_AIC_IOE_DIRECTION,
 	},
+#endif
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
 
@@ -284,8 +298,12 @@ const struct charger_config_t chg_chips[] = {
 void board_overcurrent_event(int port, int is_overcurrented)
 {
 	/* Port 0 & 1 and 2 & 3 share same line for over current indication */
+#if defined(BOARD_ADLRVPP_ITE)
 	int ioex = port < TYPE_C_PORT_2 ?
 			TYPE_C_PORT_1 : TYPE_C_PORT_3;
+#else
+	int ioex = TYPE_C_PORT_1;
+#endif
 
 	if (is_overcurrented)
 		pca9675_update_pins(ioex, TCPC_AIC_IOE_OC, 0);
@@ -370,9 +388,11 @@ static void tcpc_aic_init(void)
 	/* Default set the SBU lines to AUX mode on both the TCPC-AIC */
 	board_connect_c0_sbu_deferred();
 
+#if defined(BOARD_ADLRVPP_ITE)
 	 /* Only TCPC-0 can do CCD or BSSB, Default set SBU lines to AUX */
 	pca9675_update_pins(TYPE_C_PORT_2, 0,
 		TCPC_AIC_IOE_USB_MUX_CNTRL_1 | TCPC_AIC_IOE_USB_MUX_CNTRL_0);
+#endif
 }
 DECLARE_HOOK(HOOK_INIT, tcpc_aic_init, HOOK_PRIO_INIT_PCA9675);
 
diff --git a/board/adlrvpp_ite/board.h b/board/adlrvpp_ite/board.h
index bdfd36e774..fb8dc0f048 100644
--- a/board/adlrvpp_ite/board.h
+++ b/board/adlrvpp_ite/board.h
@@ -78,15 +78,21 @@
 #define PORT80_I2C_ADDR		MAX695X_I2C_ADDR1_FLAGS
 
 /* USB PD config */
+#if defined(BOARD_ADLRVPP_ITE)
 #define CONFIG_USB_PD_PORT_MAX_COUNT 4
+#else
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#endif
 #define CONFIG_USB_MUX_VIRTUAL
 #define PD_MAX_POWER_MW              100000
 
 /* USB-C I2C */
 #define I2C_PORT_TYPEC_0		IT83XX_I2C_CH_C
 #define I2C_PORT_TYPEC_1		IT83XX_I2C_CH_F
+#if defined(BOARD_ADLRVPP_ITE)
 #define I2C_PORT_TYPEC_2		IT83XX_I2C_CH_E
 #define I2C_PORT_TYPEC_3		IT83XX_I2C_CH_D
+#endif
 
 /* TCPC AIC config */
 /* Support NXP PCA9675 I/O expander. */
@@ -116,8 +122,10 @@
 #define CONFIG_USBC_RETIMER_INTEL_BB
 #define I2C_PORT0_BB_RETIMER_ADDR	0x50
 #define I2C_PORT1_BB_RETIMER_ADDR	0x51
+#if defined(BOARD_ADLRVPP_ITE)
 #define I2C_PORT2_BB_RETIMER_ADDR	0x52
 #define I2C_PORT3_BB_RETIMER_ADDR	0x53
+#endif
 
 /* Enable VCONN */
 #define CONFIG_USBC_VCONN
@@ -144,16 +152,20 @@ enum adlrvp_i2c_channel {
 	I2C_CHAN_BATT_CHG,
 	I2C_CHAN_TYPEC_0,
 	I2C_CHAN_TYPEC_1,
+#if defined(BOARD_ADLRVPP_ITE)
 	I2C_CHAN_TYPEC_2,
 	I2C_CHAN_TYPEC_3,
+#endif
 	I2C_CHAN_COUNT,
 };
 
 enum adlrvp_charge_ports {
 	TYPE_C_PORT_0,
 	TYPE_C_PORT_1,
+#if defined(BOARD_ADLRVPP_ITE)
 	TYPE_C_PORT_2,
 	TYPE_C_PORT_3,
+#endif
 };
 
 enum battery_type {
diff --git a/board/adlrvpp_ite/gpio.inc b/board/adlrvpp_ite/gpio.inc
index 584ca61ac4..8dc31a7fae 100644
--- a/board/adlrvpp_ite/gpio.inc
+++ b/board/adlrvpp_ite/gpio.inc
@@ -45,13 +45,23 @@ GPIO_INT(UART_SERVO_TX_EC_RX,	PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interr
 UNIMPLEMENTED(USBC_TCPC_ALRT_P0)
 GPIO(NC_USBC_TCPC_ALRT_P0,	PIN(I, 7), GPIO_INPUT)
 GPIO_INT(USBC_TCPC_ALRT_P1,	PIN(G, 0), GPIO_INT_BOTH, tcpc_alert_event)
+#if defined(BOARD_ADLRVPP_ITE)
 GPIO_INT(USBC_TCPC_ALRT_P2,	PIN(J, 1), GPIO_INT_BOTH, tcpc_alert_event)
 GPIO_INT(USBC_TCPC_ALRT_P3,	PIN(J, 3), GPIO_INT_BOTH, tcpc_alert_event)
+#else /* BOARD_ADLRVPM_ITE */
+GPIO(USBC_TCPC_ALRT_P2,		PIN(J, 1), GPIO_INPUT)
+GPIO(USBC_TCPC_ALRT_P3,		PIN(J, 3), GPIO_INPUT)
+#endif
 
+GPIO_INT(USBC_TCPC_PPC_ALRT_P0, PIN(J, 5), GPIO_INT_BOTH, ppc_interrupt)
 GPIO_INT(USBC_TCPC_PPC_ALRT_P1, PIN(C, 4), GPIO_INT_BOTH, ppc_interrupt)
+#if defined(BOARD_ADLRVPP_ITE)
 GPIO_INT(USBC_TCPC_PPC_ALRT_P2, PIN(E, 5), GPIO_INT_BOTH, ppc_interrupt)
 GPIO_INT(USBC_TCPC_PPC_ALRT_P3, PIN(E, 6), GPIO_INT_BOTH, ppc_interrupt)
-GPIO_INT(USBC_TCPC_PPC_ALRT_P0, PIN(J, 5), GPIO_INT_BOTH, ppc_interrupt)
+#else /* BOARD_ADLRVPM_ITE */
+GPIO(USBC_TCPC_PPC_ALRT_P2,	PIN(E, 5), GPIO_INPUT)
+GPIO(USBC_TCPC_PPC_ALRT_P3,	PIN(E, 6), GPIO_INPUT)
+#endif
 
 #ifndef CONFIG_HOSTCMD_ESPI
 GPIO_INT(ESPI_RST_R,		PIN(D, 2), GPIO_INPUT)