diff options
author | Shelley Chen <shchen@google.com> | 2019-11-20 23:45:32 -0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2019-11-22 10:17:21 +0000 |
commit | 5b30bc23812eb0d54789851a5b951b364d28f635 (patch) | |
tree | 71a81b0a6a7ddeb24ff6aed467cc8f94cf841864 /board/akemi | |
parent | e73c807595eba1bc1a1b575fb12f252522cffca3 (diff) | |
download | chrome-ec-5b30bc23812eb0d54789851a5b951b364d28f635.tar.gz |
all hatch variants: Assign SYS_RST_ODL to GPIOC5
There is an error where SYS_RST_ODL is assigned to GPIO02 where it is
actually assigned to GPIOC5 in the schematics. This should cause AP
reset to fail from the ec console.
BUG=b:141476349
BRANCH=hatch
TEST=None (I don't have a hatch board to test this out on)
Change-Id: I855a65489ce974ee92be4bf51a83d5af40e4e2da
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928421
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'board/akemi')
-rw-r--r-- | board/akemi/gpio.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/akemi/gpio.inc b/board/akemi/gpio.inc index 14c44fd4f6..247724b2d2 100644 --- a/board/akemi/gpio.inc +++ b/board/akemi/gpio.inc @@ -41,7 +41,7 @@ GPIO_INT(USB_C1_BC12_INT_ODL, PIN(E, 4), GPIO_INT_FALLING, bc12_interrupt) GPIO_INT(EC_VOLDN_BTN_ODL, PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) GPIO_INT(EC_VOLUP_BTN_ODL, PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) -GPIO(SYS_RESET_L, PIN(0, 2), GPIO_ODR_HIGH) /* SYS_RST_ODL */ +GPIO(SYS_RESET_L, PIN(C, 5), GPIO_ODR_HIGH) /* SYS_RST_ODL */ GPIO(ENTERING_RW, PIN(E, 3), GPIO_OUT_LOW) /* EC_ENTERING_RW */ GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */ GPIO(PCH_PWRBTN_L, PIN(C, 1), GPIO_ODR_HIGH) /* EC_PCH_PWR_BTN_ODL */ |