diff options
| author | Caveh Jalali <caveh@chromium.org> | 2021-03-04 23:39:50 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-16 03:56:37 +0000 |
| commit | 897d3dc804818672eeba5c74338a0063457bd329 (patch) | |
| tree | bcb27d7bf3cc9f514194892a57662dbb4eeed3d2 /board/brya/generated-gpio.inc | |
| parent | b3daa50ee2a354d4ccee3c1b4eb893dafbf20d98 (diff) | |
| download | chrome-ec-897d3dc804818672eeba5c74338a0063457bd329.tar.gz | |
brya: Update auto-generated GPIO list
This refreshes the generated GPIO list based on updates in the main GPIO
definition spreadsheet. The only difference is that GPIOs are no longer
marked as "alternate" even when GPIO functionality is the alternate
function of a pin. The NPCX support code automatically puts all declared
GPIO pins into GPIO mode even when that is a pin's alternate function.
BRANCH=none
BUG=b:173575131
TEST=buildall passes
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Change-Id: Ib7ba12f45407f86dc5fac6a75f68dee14be02514
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2738548
Reviewed-by: Keith Short <keithshort@chromium.org>
Diffstat (limited to 'board/brya/generated-gpio.inc')
| -rw-r--r-- | board/brya/generated-gpio.inc | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/board/brya/generated-gpio.inc b/board/brya/generated-gpio.inc index 83ad1f3a31..5728cd39de 100644 --- a/board/brya/generated-gpio.inc +++ b/board/brya/generated-gpio.inc @@ -114,19 +114,6 @@ ALTERNATE(PIN_MASK(8, 0x04), 0, MODULE_KB, GPIO_ODR_HIGH) /* KSO14/GPIO82 */ ALTERNATE(PIN_MASK(8, 0x20), 0, MODULE_KB, GPIO_OUT_LOW) /* PSL_OUT&GPIO85/GPO85 */ /* GPIO alternate functions */ -ALTERNATE(PIN_MASK(0, 0x01), 0, MODULE_GPIO, GPIO_INPUT | GPIO_INT_BOTH) /* PSL_IN2_L&GPI00/GPIO00 */ -ALTERNATE(PIN_MASK(0, 0x08), 0, MODULE_GPIO, GPIO_OUT_LOW) /* KSO16/GPIO03 */ -ALTERNATE(PIN_MASK(7, 0x04), 0, MODULE_GPIO, GPIO_OUT_LOW) /* PWRGD/GPIO72 */ -ALTERNATE(PIN_MASK(8, 0x02), 0, MODULE_GPIO, GPIO_INPUT) /* PECI_DATA/GPIO81 */ -ALTERNATE(PIN_MASK(8, 0x08), 0, MODULE_GPIO, GPIO_INPUT | GPIO_INT_BOTH) /* KSO15/GPIO83 */ -ALTERNATE(PIN_MASK(9, 0x20), 0, MODULE_GPIO, GPIO_INPUT) /* SPIP_MISO/GPIO95 */ -ALTERNATE(PIN_MASK(9, 0x40), 0, MODULE_GPIO, GPIO_ODR_LOW) /* F_DIO1/GPIO96 */ -ALTERNATE(PIN_MASK(A, 0x07), 0, MODULE_GPIO, GPIO_INPUT | GPIO_INT_BOTH) /* SPIP_SCLK/GPIOA1, F_CS0_L/GPIOA0, F_SCLK/GPIOA2 */ -ALTERNATE(PIN_MASK(A, 0x10), 0, MODULE_GPIO, GPIO_ODR_LOW) /* F_DIO0/GPIOA4/TB1 */ -ALTERNATE(PIN_MASK(A, 0x08), 0, MODULE_GPIO, GPIO_OUT_LOW) /* SPIP_MOSI/GPIOA3 */ -ALTERNATE(PIN_MASK(B, 0x02), 0, MODULE_GPIO, GPIO_INPUT | GPIO_INT_BOTH) /* KSO17/GPIOB1/CR_SIN4 */ -ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_GPIO, GPIO_INPUT) /* PSL_IN1_L&GPID2/GPIOD2 */ -ALTERNATE(PIN_MASK(D, 0x80), 0, MODULE_GPIO, GPIO_OUT_LOW) /* PSL_GPO/GPOD7 */ /* Unused Pins */ UNUSED(PIN(D, 6)) /* GPOD6/CR_SOUT3/SHDF_ESPI_L */ |