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authorCaveh Jalali <caveh@chromium.org>2021-06-16 22:20:55 -0700
committerCommit Bot <commit-bot@chromium.org>2021-06-29 18:00:29 +0000
commit51a8b8fba91e2eb24b50bd26807174d8758c73f0 (patch)
tree3a7180ac580871a931577b5a662d081cc8ea52e6 /board/brya/generated-gpio.inc
parent3cf5da6e679ae7a3a6bafb1612b5654897416e22 (diff)
downloadchrome-ec-51a8b8fba91e2eb24b50bd26807174d8758c73f0.tar.gz
brya: Config USB_C0_C2_TCPC_RST_ODL as ODR
This configures USB_C0_C2_TCPC_RST_ODL as ODR_LOW instead of driven low since this signal has a board level pull-up. BRANCH=none BUG=b:183452273 TEST=boots on board ID 1 Change-Id: Ib199a88349242489481896cfbe8fcbdb303810b9 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977474 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
Diffstat (limited to 'board/brya/generated-gpio.inc')
-rw-r--r--board/brya/generated-gpio.inc4
1 files changed, 2 insertions, 2 deletions
diff --git a/board/brya/generated-gpio.inc b/board/brya/generated-gpio.inc
index 37988346ad..bb72861263 100644
--- a/board/brya/generated-gpio.inc
+++ b/board/brya/generated-gpio.inc
@@ -71,7 +71,7 @@ GPIO(EN_S5_RAILS, PIN(B, 6), GPIO_OUT_LOW)
GPIO(IMVP9_VRRDY_OD, PIN(4, 3), GPIO_INPUT)
GPIO(PCH_PWROK, PIN(7, 2), GPIO_OUT_LOW)
GPIO(SYS_RST_ODL, PIN(C, 5), GPIO_ODR_HIGH)
-GPIO(USB_C0_C2_TCPC_RST_ODL, PIN(A, 7), GPIO_OUT_LOW)
+GPIO(USB_C0_C2_TCPC_RST_ODL, PIN(A, 7), GPIO_ODR_LOW)
GPIO(USB_C1_FRS_EN, PIN(9, 4), GPIO_OUT_LOW)
GPIO(USB_C1_RST_ODL, PIN(9, 6), GPIO_ODR_LOW)
GPIO(USB_C1_RT_RST_R_ODL, PIN(0, 2), GPIO_ODR_LOW)
@@ -119,6 +119,6 @@ ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
UNUSED(PIN(D, 6)) /* GPOD6/CR_SOUT3/SHDF_ESPI_L */
UNUSED(PIN(3, 2)) /* GPO32/TRIS_L */
UNUSED(PIN(3, 5)) /* GPO35/CR_SOUT4/TEST_L */
-UNUSED(PIN(6, 6)) /* GPO66/ARM_L_x86 */
+UNUSED(PIN(6, 6)) /* GPIO66 */
/* Pre-configured PSL balls: J8 K6 */