brya: support board ID 2 IO expander GPIO shuffle

This updates the IO expander GPIO definitions for board ID 2.

We also need to support board ID 1, so the legacy definitions are
captured in the IOEX table as additional IO expanders. All code that
accesses the IO expander table knows which entries are valid for a given
board ID and all entries are market DISABLED at compile time, so there
are no conflicts.

BRANCH=none
BUG=b:190867210
TEST=boots on board ID 1, can read BB registers when USB device is
	plugged in.

Change-Id: Ief3a70d08770e77120efa52f214cc1d81e6ebe08
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977477
Reviewed-by: Boris Mittelberg <bmbm@google.com>

3 files changed, 60 insertions, 13 deletions

diff --git a/board/brya/board.h b/board/brya/board.h
index c24874f30e..d7ca163bad 100644
--- a/board/brya/board.h
+++ b/board/brya/board.h
@@ -85,7 +85,7 @@
 
 #define CONFIG_IO_EXPANDER
 #define CONFIG_IO_EXPANDER_NCT38XX
-#define CONFIG_IO_EXPANDER_PORT_COUNT		2
+#define CONFIG_IO_EXPANDER_PORT_COUNT		4
 
 #define CONFIG_USB_PD_TCPM_PS8815
 #define CONFIG_USBC_RETIMER_INTEL_BB
@@ -236,6 +236,8 @@ enum sensor_id {
 enum ioex_port {
 	IOEX_C0_NCT38XX = 0,
 	IOEX_C2_NCT38XX,
+	IOEX_ID_1_C0_NCT38XX,
+	IOEX_ID_1_C2_NCT38XX,
 	IOEX_PORT_COUNT
 };
 
diff --git a/board/brya/gpio.inc b/board/brya/gpio.inc
index 4b243979dd..79a97b0475 100644
--- a/board/brya/gpio.inc
+++ b/board/brya/gpio.inc
@@ -45,12 +45,30 @@ GPIO(ID_1_EC_BATT_PRES_ODL,       PIN(E, 1), GPIO_INPUT)
  */
 GPIO(ID_1_USB_C0_C2_TCPC_RST_ODL, PIN(3, 4), GPIO_ODR_LOW)
 
-IOEX(ID_1_USB_C0_RT_RST_ODL, EXPIN(IOEX_C0_NCT38XX, 0, 2), GPIO_ODR_LOW)
-IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_LOW)
-IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_ODR_HIGH)
+/* Board ID 1 IO expander configuration */
+
+IOEX(ID_1_USB_C0_RT_RST_ODL, EXPIN(IOEX_ID_1_C0_NCT38XX, 0, 2), GPIO_ODR_LOW)
+/* GPIO03_P1 to PU */
+IOEX(ID_1_USB_C0_FRS_EN,     EXPIN(IOEX_ID_1_C0_NCT38XX, 0, 4), GPIO_LOW)
+IOEX(ID_1_USB_C0_OC_ODL,     EXPIN(IOEX_ID_1_C0_NCT38XX, 0, 6), GPIO_ODR_HIGH)
+/* GPIO07_P1 to PU */
+
+IOEX(ID_1_USB_C2_RT_RST_ODL, EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 2), GPIO_ODR_LOW)
+/* GPIO03_P2 to PU */
+IOEX(ID_1_USB_C2_FRS_EN,     EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 4), GPIO_LOW)
+IOEX(ID_1_USB_C1_OC_ODL,     EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 6), GPIO_ODR_HIGH)
+IOEX(ID_1_USB_C2_OC_ODL,     EXPIN(IOEX_ID_1_C2_NCT38XX, 0, 7), GPIO_ODR_HIGH)
+
+/* Board ID 2 IO expander configuration */
+
+/* GPIO02_P2 to PU */
+/* GPIO03_P2 to PU */
+IOEX(USB_C0_OC_ODL,          EXPIN(IOEX_C0_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C0_FRS_EN,          EXPIN(IOEX_C0_NCT38XX, 0, 6), GPIO_LOW)
 IOEX(USB_C0_RT_RST_ODL,      EXPIN(IOEX_C0_NCT38XX, 0, 7), GPIO_ODR_LOW)
 
 IOEX(USB_C2_RT_RST_ODL,      EXPIN(IOEX_C2_NCT38XX, 0, 2), GPIO_ODR_LOW)
-IOEX(USB_C2_FRS_EN,          EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_LOW)
-IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_ODR_HIGH)
-IOEX(USB_C2_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 7), GPIO_ODR_HIGH)
+IOEX(USB_C1_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 3), GPIO_ODR_HIGH)
+IOEX(USB_C2_OC_ODL,          EXPIN(IOEX_C2_NCT38XX, 0, 4), GPIO_ODR_HIGH)
+IOEX(USB_C2_FRS_EN,          EXPIN(IOEX_C2_NCT38XX, 0, 6), GPIO_LOW)
+/* GPIO07_P2 to PU */
diff --git a/board/brya/usbc_config.c b/board/brya/usbc_config.c
index 4c84b814aa..802296a66c 100644
--- a/board/brya/usbc_config.c
+++ b/board/brya/usbc_config.c
@@ -184,6 +184,18 @@ struct ioexpander_config_t ioex_config[] = {
 		.drv = &nct38xx_ioexpander_drv,
 		.flags = IOEX_FLAGS_DISABLED,
 	},
+	[IOEX_ID_1_C0_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DISABLED,
+	},
+	[IOEX_ID_1_C2_NCT38XX] = {
+		.i2c_host_port = I2C_PORT_USB_C0_C2_TCPC,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+		.flags = IOEX_FLAGS_DISABLED,
+	},
 };
 BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT);
 
@@ -208,7 +220,10 @@ __override int bb_retimer_power_enable(const struct usb_mux *me, bool enable)
 		else
 			rst_signal = IOEX_USB_C0_RT_RST_ODL;
 	} else if (me->usb_port == USBC_PORT_C2) {
-		rst_signal = IOEX_USB_C2_RT_RST_ODL;
+		if (get_board_id() == 1)
+			rst_signal = IOEX_ID_1_USB_C2_RT_RST_ODL;
+		else
+			rst_signal = IOEX_USB_C2_RT_RST_ODL;
 	} else {
 		return EC_ERROR_INVAL;
 	}
@@ -288,17 +303,29 @@ void board_reset_pd_mcu(void)
 	msleep(50);
 }
 
-static void board_tcpc_init(void)
+static void enable_ioex(int ioex)
 {
-	int i;
+	ioex_config[ioex].flags &= ~IOEX_FLAGS_DISABLED;
+	ioex_init(ioex);
+}
 
+static void board_tcpc_init(void)
+{
 	/* Don't reset TCPCs after initial reset */
 	if (!system_jumped_late()) {
 		board_reset_pd_mcu();
 
-		for (i = 0; i < CONFIG_IO_EXPANDER_PORT_COUNT; ++i) {
-			ioex_config[i].flags &= ~IOEX_FLAGS_DISABLED;
-			ioex_init(i);
+		/*
+		 * These IO expander pins are implemented using the
+		 * C0/C2 TCPC, so they must be set up after the TCPC has
+		 * been taken out of reset.
+		 */
+		if (get_board_id() == 1) {
+			enable_ioex(IOEX_ID_1_C0_NCT38XX);
+			enable_ioex(IOEX_ID_1_C2_NCT38XX);
+		} else {
+			enable_ioex(IOEX_C0_NCT38XX);
+			enable_ioex(IOEX_C2_NCT38XX);
 		}
 	}