grunt: Move common code to baseboard

Move code that will be common to Grunt and Careena to baseboard
to avoid duplication when creating the Careena board.

Add Careena board files. These are currently just a copy of Grunt
and will be modified for Careena next.

BUG=b:79704826
BRANCH=none
TEST=Grunt still boots ok.

Change-Id: I6dd0035bdd62e92a7f3664120fc6ac3f23a0af4d
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1070988

6 files changed, 563 insertions, 0 deletions

diff --git a/board/careena/board.c b/board/careena/board.c
new file mode 100644
index 0000000000..cdf0652307
--- /dev/null
+++ b/board/careena/board.c
@@ -0,0 +1,281 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Careena board-specific configuration */
+
+#include "adc.h"
+#include "adc_chip.h"
+#include "button.h"
+#include "charge_manager.h"
+#include "charge_state.h"
+#include "charge_state_v2.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "driver/accel_kionix.h"
+#include "driver/accel_kx022.h"
+#include "driver/accelgyro_bmi160.h"
+#include "driver/bc12/bq24392.h"
+#include "driver/led/lm3630a.h"
+#include "driver/ppc/sn5s330.h"
+#include "driver/tcpm/anx74xx.h"
+#include "driver/tcpm/ps8xxx.h"
+#include "driver/temp_sensor/sb_tsi.h"
+#include "ec_commands.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "motion_sense.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "registers.h"
+#include "switch.h"
+#include "system.h"
+#include "task.h"
+#include "tcpci.h"
+#include "temp_sensor.h"
+#include "thermistor.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+
+/*
+ * These GPIOs change pins depending on board version. They are configured
+ * in board_init.
+ */
+static enum gpio_signal gpio_usb_c1_oc_l = GPIO_USB_C1_OC_L_V2;
+static enum gpio_signal gpio_usb_c0_pd_rst_l = GPIO_USB_C0_PD_RST_L_V2;
+
+static void tcpc_alert_event(enum gpio_signal signal)
+{
+	if ((signal == GPIO_USB_C0_PD_INT_ODL) &&
+			!gpio_get_level(gpio_usb_c0_pd_rst_l))
+		return;
+
+	if ((signal == GPIO_USB_C1_PD_INT_ODL) &&
+			!gpio_get_level(GPIO_USB_C1_PD_RST_L))
+		return;
+
+#ifdef HAS_TASK_PDCMD
+	/* Exchange status with TCPCs */
+	host_command_pd_send_status(PD_CHARGE_NO_CHANGE);
+#endif
+}
+
+#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
+static void anx74xx_cable_det_handler(void)
+{
+	int cable_det = gpio_get_level(GPIO_USB_C0_CABLE_DET);
+	int reset_n = gpio_get_level(gpio_usb_c0_pd_rst_l);
+
+	/*
+	 * A cable_det low->high transition was detected. If following the
+	 * debounce time, cable_det is high, and reset_n is low, then ANX3429 is
+	 * currently in standby mode and needs to be woken up. Set the
+	 * TCPC_RESET event which will bring the ANX3429 out of standby
+	 * mode. Setting this event is gated on reset_n being low because the
+	 * ANX3429 will always set cable_det when transitioning to normal mode
+	 * and if in normal mode, then there is no need to trigger a tcpc reset.
+	 */
+	if (cable_det && !reset_n)
+		task_set_event(TASK_ID_PD_C0, PD_EVENT_TCPC_RESET, 0);
+}
+DECLARE_DEFERRED(anx74xx_cable_det_handler);
+
+void anx74xx_cable_det_interrupt(enum gpio_signal signal)
+{
+	/* debounce for 2 msec */
+	hook_call_deferred(&anx74xx_cable_det_handler_data, (2 * MSEC));
+}
+#endif
+
+static void ppc_interrupt(enum gpio_signal signal)
+{
+	int port = (signal == GPIO_USB_C0_SWCTL_INT_ODL) ? 0 : 1;
+
+	sn5s330_interrupt(port);
+}
+
+#include "gpio_list.h"
+
+/* I2C port map. */
+const struct i2c_port_t i2c_ports[] = {
+	{"power",   I2C_PORT_POWER,   100, GPIO_I2C0_SCL, GPIO_I2C0_SDA},
+	{"tcpc0",   I2C_PORT_TCPC0,   400, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
+	{"tcpc1",   I2C_PORT_TCPC1,   400, GPIO_I2C2_SCL, GPIO_I2C2_SDA},
+	{"thermal", I2C_PORT_THERMAL, 400, GPIO_I2C3_SCL, GPIO_I2C3_SDA},
+	{"kblight", I2C_PORT_KBLIGHT, 100, GPIO_I2C5_SCL, GPIO_I2C5_SDA},
+	{"sensor",  I2C_PORT_SENSOR,  400, GPIO_I2C7_SCL, GPIO_I2C7_SDA},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+static void board_init(void)
+{
+	if (system_get_board_version() < 2) {
+		/*
+		 * These GPIOs change pins depending on board version. Change
+		 * them here from the V2 pin to the V0 pin.
+		 */
+		gpio_usb_c1_oc_l = GPIO_USB_C1_OC_L_V0;
+		gpio_usb_c0_pd_rst_l = GPIO_USB_C0_PD_RST_L_V0;
+	} else {
+		/* Alternate functions for board version 2 only. */
+		gpio_set_alternate_function(GPIO_F, 0x02, 1); /* ADC8 */
+		gpio_set_alternate_function(GPIO_0, 0x10, 0); /* KSO_13 */
+		gpio_set_alternate_function(GPIO_8, 0x04, 0); /* KSO_14 */
+	}
+
+	/* Now that we know which pin to use, set the correct output mode. */
+	gpio_set_flags(gpio_usb_c1_oc_l, GPIO_OUT_HIGH);
+	gpio_set_flags(gpio_usb_c0_pd_rst_l, GPIO_OUT_HIGH);
+
+	/* Enable Gyro interrupts */
+	gpio_enable_interrupt(GPIO_6AXIS_INT_L);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
+
+void board_overcurrent_event(int port)
+{
+	enum gpio_signal signal = (port == 0) ? GPIO_USB_C0_OC_L
+					      : gpio_usb_c1_oc_l;
+
+	gpio_set_level(signal, 0);
+
+	CPRINTS("p%d: overcurrent!", port);
+}
+
+void board_tcpc_init(void)
+{
+	int count = 0;
+	int port;
+
+	/* Wait for disconnected battery to wake up */
+	while (battery_hw_present() == BP_YES &&
+	       battery_is_present() == BP_NO) {
+		usleep(100 * MSEC);
+		/* Give up waiting after 1 second */
+		if (++count > 10)
+			break;
+	}
+
+	/* Only reset TCPC if not sysjump */
+	if (!system_jumped_to_this_image())
+		board_reset_pd_mcu();
+
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_SWCTL_INT_ODL);
+	if (system_get_board_version() < 2)
+		gpio_enable_interrupt(GPIO_USB_C1_SWCTL_INT_ODL_V0);
+	else
+		gpio_enable_interrupt(GPIO_USB_C1_SWCTL_INT_ODL_V2);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PD_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PD_INT_ODL);
+
+#ifdef CONFIG_USB_PD_TCPC_LOW_POWER
+	/* Enable CABLE_DET interrupt for ANX3429 wake from standby */
+	gpio_enable_interrupt(GPIO_USB_C0_CABLE_DET);
+#endif
+	/*
+	 * Initialize HPD to low; after sysjump SOC needs to see
+	 * HPD pulse to enable video path
+	 */
+	for (port = 0; port < CONFIG_USB_PD_PORT_COUNT; port++) {
+		const struct usb_mux *mux = &usb_muxes[port];
+
+		mux->hpd_update(port, 0, 0);
+	}
+}
+DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_I2C + 1);
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	if (!gpio_get_level(GPIO_USB_C0_PD_INT_ODL)) {
+		if (gpio_get_level(gpio_usb_c0_pd_rst_l))
+			status |= PD_STATUS_TCPC_ALERT_0;
+	}
+
+	if (!gpio_get_level(GPIO_USB_C1_PD_INT_ODL)) {
+		if (gpio_get_level(GPIO_USB_C1_PD_RST_L))
+			status |= PD_STATUS_TCPC_ALERT_1;
+	}
+
+	return status;
+}
+
+/**
+ * Power on (or off) a single TCPC.
+ * minimum on/off delays are included.
+ *
+ * @param port	Port number of TCPC.
+ * @param mode	0: power off, 1: power on.
+ */
+void board_set_tcpc_power_mode(int port, int mode)
+{
+	if (port != USB_PD_PORT_ANX74XX)
+		return;
+
+	switch (mode) {
+	case ANX74XX_NORMAL_MODE:
+		gpio_set_level(GPIO_EN_USB_C0_TCPC_PWR, 1);
+		msleep(ANX74XX_PWR_H_RST_H_DELAY_MS);
+		gpio_set_level(gpio_usb_c0_pd_rst_l, 1);
+		break;
+	case ANX74XX_STANDBY_MODE:
+		gpio_set_level(gpio_usb_c0_pd_rst_l, 0);
+		msleep(ANX74XX_RST_L_PWR_L_DELAY_MS);
+		gpio_set_level(GPIO_EN_USB_C0_TCPC_PWR, 0);
+		msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
+		break;
+	default:
+		break;
+	}
+}
+
+void board_reset_pd_mcu(void)
+{
+	/* Assert reset to TCPC1 (ps8751) */
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 0);
+
+	/* Assert reset to TCPC0 (anx3429) */
+	gpio_set_level(gpio_usb_c0_pd_rst_l, 0);
+
+	/* TCPC1 (ps8751) requires 1ms reset down assertion */
+	msleep(MAX(1, ANX74XX_RST_L_PWR_L_DELAY_MS));
+
+	/* Deassert reset to TCPC1 */
+	gpio_set_level(GPIO_USB_C1_PD_RST_L, 1);
+	/* Disable TCPC0 power */
+	gpio_set_level(GPIO_EN_USB_C0_TCPC_PWR, 0);
+
+	/*
+	 * anx3429 requires 10ms reset/power down assertion
+	 */
+	msleep(ANX74XX_PWR_L_PWR_H_DELAY_MS);
+	board_set_tcpc_power_mode(USB_PD_PORT_ANX74XX, 1);
+}
+
+static void board_kblight_init(void)
+{
+	/*
+	 * Enable keyboard backlight. This needs to be done here because
+	 * the chip doesn't have power until PP3300_S0 comes up.
+	 */
+	gpio_set_level(GPIO_KB_BL_EN, 1);
+	lm3630a_poweron();
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, board_kblight_init, HOOK_PRIO_DEFAULT);
diff --git a/board/careena/board.h b/board/careena/board.h
new file mode 100644
index 0000000000..7f0906ddec
--- /dev/null
+++ b/board/careena/board.h
@@ -0,0 +1,44 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Careena board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "baseboard.h"
+
+/*
+ * By default, enable all console messages excepted HC, ACPI and event:
+ * The sensor stack is generating a lot of activity.
+ */
+#define CC_DEFAULT     (CC_ALL & ~(CC_MASK(CC_EVENTS) | CC_MASK(CC_LPC)))
+#undef CONFIG_HOSTCMD_DEBUG_MODE
+#define CONFIG_HOSTCMD_DEBUG_MODE HCDEBUG_OFF
+
+#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
+
+/* Power and battery LEDs */
+#define CONFIG_LED_COMMON
+#define CONFIG_CMD_LEDTEST
+
+#undef CONFIG_LED_PWM_NEAR_FULL_COLOR
+#undef CONFIG_LED_PWM_CHARGE_ERROR_COLOR
+#undef CONFIG_LED_PWM_SOC_ON_COLOR
+#undef CONFIG_LED_PWM_SOC_SUSPEND_COLOR
+
+#define CONFIG_LED_PWM_NEAR_FULL_COLOR EC_LED_COLOR_BLUE
+#define CONFIG_LED_PWM_CHARGE_ERROR_COLOR EC_LED_COLOR_AMBER
+#define CONFIG_LED_PWM_SOC_ON_COLOR EC_LED_COLOR_BLUE
+#define CONFIG_LED_PWM_SOC_SUSPEND_COLOR EC_LED_COLOR_BLUE
+
+#define CONFIG_LED_PWM_COUNT 1
+
+#define I2C_PORT_KBLIGHT NPCX_I2C_PORT5_0
+
+/* KB backlight driver */
+#define CONFIG_LED_DRIVER_LM3630A
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/careena/build.mk b/board/careena/build.mk
new file mode 100644
index 0000000000..9620af3152
--- /dev/null
+++ b/board/careena/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2015 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m6f
+BASEBOARD:=grunt
+
+board-y=board.o led.o
diff --git a/board/careena/ec.tasklist b/board/careena/ec.tasklist
new file mode 100644
index 0000000000..be1dbcc21f
--- /dev/null
+++ b/board/careena/ec.tasklist
@@ -0,0 +1,37 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ *
+ * For USB PD tasks, IDs must be in consecutive order and correspond to
+ * the port which they are for. See TASK_ID_TO_PD_PORT() macro.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(PDCMD, pd_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/careena/gpio.inc b/board/careena/gpio.inc
new file mode 100644
index 0000000000..bfdbd0e376
--- /dev/null
+++ b/board/careena/gpio.inc
@@ -0,0 +1,121 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+GPIO_INT(USB_C0_PD_INT_ODL,	PIN(A, 0), GPIO_INT_FALLING,			tcpc_alert_event)
+GPIO_INT(USB_C1_PD_INT_ODL,	PIN(F, 5), GPIO_INT_FALLING,			tcpc_alert_event)
+GPIO_INT(USB_C0_SWCTL_INT_ODL,	PIN(0, 3), GPIO_INT_FALLING,			ppc_interrupt)
+GPIO_INT(USB_C1_SWCTL_INT_ODL_V0, PIN(0, 4), GPIO_INT_FALLING,			ppc_interrupt)
+GPIO_INT(USB_C1_SWCTL_INT_ODL_V2, PIN(D, 4), GPIO_INT_FALLING,			ppc_interrupt)
+GPIO_INT(PCH_SLP_S3_L,		PIN(A, 6), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(PCH_SLP_S5_L,		PIN(A, 3), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(S0_PGOOD,		PIN(F, 4), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(S5_PGOOD,		PIN(6, 3), GPIO_INT_BOTH | GPIO_PULL_UP,	power_signal_interrupt)
+GPIO_INT(POWER_BUTTON_L,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
+GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)
+GPIO_INT(AC_PRESENT,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
+GPIO_INT(WP_L,			PIN(A, 1), GPIO_INT_BOTH,			switch_interrupt)
+GPIO_INT(VOLUME_DOWN_L,		PIN(7, 0), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
+GPIO_INT(VOLUME_UP_L,		PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
+GPIO_INT(USB_C0_CABLE_DET,	PIN(3, 7), GPIO_INT_RISING,			anx74xx_cable_det_interrupt)
+GPIO_INT(6AXIS_INT_L,		PIN(8, 6), GPIO_INT_FALLING | GPIO_SEL_1P8V,	bmi160_interrupt)
+
+GPIO(EN_PWR_A,			PIN(E, 2), GPIO_OUT_LOW)			/* Enable Power */
+GPIO(EN_PP1800_SENSOR,		PIN(6, 7), GPIO_OUT_LOW)			/* Enable Power */
+GPIO(ENABLE_BACKLIGHT_L,	PIN(D, 3), GPIO_OUT_HIGH)			/* Enable Backlight */
+GPIO(PCH_RSMRST_L,		PIN(C, 2), GPIO_OUT_LOW)			/* RSMRST# to SOC */
+GPIO(PCH_PWRBTN_L,		PIN(C, 1), GPIO_OUT_HIGH)			/* Power Button to SOC */
+GPIO(PCH_WAKE_L,		PIN(7, 4), GPIO_OUT_HIGH)			/* Wake SOC */
+GPIO(PCH_RCIN_L,		PIN(0, 2), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
+GPIO(CCD_MODE_ODL,		PIN(E, 3), GPIO_INPUT)				/* Case Closed Debug Mode */
+GPIO(ENTERING_RW,		PIN(E, 1), GPIO_OUT_LOW)			/* EC Entering RW */
+GPIO(EC_BATT_PRES_ODL,		PIN(E, 5), GPIO_INPUT | GPIO_PULL_UP)		/* Battery Present */
+GPIO(PCH_SYS_PWROK,		PIN(D, 6), GPIO_OUT_LOW)			/* Power OK to SOC */
+GPIO(EC_APU_RST,		PIN(E, 4), GPIO_INPUT)				/* Reset to SOC */
+GPIO(CPU_PROCHOT,		PIN(3, 4), GPIO_INPUT | GPIO_SEL_1P8V)		/* PROCHOT to SOC */
+GPIO(APU_ALERT_L,		PIN(A, 2), GPIO_INPUT)				/* Alert to SOC */
+GPIO(3AXIS_INT_L,		PIN(5, 0), GPIO_INPUT | GPIO_SEL_1P8V)		/* 3 Axis Accel */
+GPIO(KB_BL_EN,			PIN(F, 2), GPIO_OUT_LOW)			/* Enable KB Backlight */
+
+/* We don't have 5V rail control but the BQ24392 driver expects the GPIO */
+UNIMPLEMENTED(EN_PP5000)
+
+/* I2C pins - these will be reconfigured for alternate function below */
+GPIO(I2C0_SCL,			PIN(B, 5), GPIO_INPUT)				/* EC_I2C_POWER_SCL */
+GPIO(I2C0_SDA,			PIN(B, 4), GPIO_INPUT)				/* EC_I2C_POWER_SDA */
+GPIO(I2C1_SCL,			PIN(9, 0), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SCL */
+GPIO(I2C1_SDA,			PIN(8, 7), GPIO_INPUT)				/* EC_I2C_USB_C0_PD_SDA */
+GPIO(I2C2_SCL,			PIN(9, 2), GPIO_INPUT)				/* EC_I2C_USB_C1_PD_SCL */
+GPIO(I2C2_SDA,			PIN(9, 1), GPIO_INPUT)				/* EC_I2C_USB_C1_PD_SDA */
+GPIO(I2C3_SCL,			PIN(D, 1), GPIO_INPUT | GPIO_SEL_1P8V)		/* APU_SIC */
+GPIO(I2C3_SDA,			PIN(D, 0), GPIO_INPUT | GPIO_SEL_1P8V)		/* APU_SID */
+GPIO(I2C5_SCL,			PIN(3, 3), GPIO_INPUT)				/* EC_I2C_EEPROM_SCL and
+										   EC_I2C_KB_BL_SCL */
+GPIO(I2C5_SDA,			PIN(3, 6), GPIO_INPUT)				/* EC_I2C_EEPROM_SDA and
+										   EC_I2C_KB_BL_SDA */
+GPIO(I2C7_SCL,			PIN(B, 3), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_SENSOR_SCL */
+GPIO(I2C7_SDA,			PIN(B, 2), GPIO_INPUT | GPIO_SEL_1P8V)		/* EC_I2C_SENSOR_SDA */
+
+/*
+ * The NPCX LPC driver configures and controls SCI and SMI,
+ * so PCH_SCI_ODL [PIN(7, 6)] and PCH_SMI_ODL [PIN(C, 6)] are
+ * not defined here as GPIOs.
+ */
+GPIO(PCH_SLP_S0_L,		PIN(A, 4), GPIO_INPUT)
+
+GPIO(EN_USB_A0_5V,		PIN(6, 1), GPIO_OUT_LOW)			/* Enable A0 5V Charging */
+GPIO(EN_USB_A1_5V,		PIN(C, 0), GPIO_OUT_LOW)			/* Enable A1 5V Charging */
+GPIO(EN_USB_C0_TCPC_PWR,	PIN(6, 0), GPIO_OUT_LOW)			/* Enable C0 TCPC Power */
+GPIO(USB_C0_OC_L,		PIN(7, 3), GPIO_OUT_HIGH)			/* C0 Over Current */
+GPIO(USB_C1_OC_L_V0,		PIN(D, 7), GPIO_INPUT)				/* C1 Over Current */
+GPIO(USB_C1_OC_L_V2,		PIN(7, 2), GPIO_INPUT)				/* C1 Over Current */
+GPIO(USB_C0_PD_RST_L_V0,	PIN(F, 1), GPIO_INPUT)				/* C0 PD Reset */
+GPIO(USB_C0_PD_RST_L_V2,	PIN(3, 2), GPIO_INPUT)				/* C0 PD Reset */
+GPIO(USB_C1_PD_RST_L,		PIN(D, 5), GPIO_OUT_HIGH)			/* C1 PD Reset */
+GPIO(USB_C0_BC12_VBUS_ON_L_V0,	PIN(8, 2), GPIO_INPUT)				/* C0 BC1.2 Power */
+GPIO(USB_C0_BC12_VBUS_ON_L_V2,	PIN(4, 0), GPIO_ODR_HIGH)			/* C0 BC1.2 Power */
+GPIO(USB_C1_BC12_VBUS_ON_L,	PIN(B, 1), GPIO_ODR_HIGH)			/* C1 BC1.2 Power */
+GPIO(USB_C0_BC12_CHG_DET,	PIN(6, 2), GPIO_INPUT)				/* C0 BC1.2 Detect */
+GPIO(USB_C1_BC12_CHG_DET,	PIN(8, 3), GPIO_INPUT)				/* C1 BC1.2 Detect */
+GPIO(USB_C0_DP_HPD,		PIN(9, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
+GPIO(USB_C1_DP_HPD,		PIN(9, 6), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
+
+/* Board ID */
+GPIO(BOARD_VERSION1,		PIN(C, 7), GPIO_INPUT)
+GPIO(BOARD_VERSION2,		PIN(9, 3), GPIO_INPUT)
+GPIO(BOARD_VERSION3,		PIN(8, 0), GPIO_INPUT)
+GPIO(SKU_ID1,			PIN(F, 0), GPIO_INPUT)
+GPIO(SKU_ID2,			PIN(4, 1), GPIO_INPUT)
+
+/* Alternate functions GPIO definitions */
+/* Cr50 requires no pull-ups on UART pins. */
+ALTERNATE(PIN_MASK(6, 0x30), 0, MODULE_UART, 0)					/* UART from EC to Servo */
+ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0)					/* I2C0 */
+ALTERNATE(PIN_MASK(9, 0x07), 1, MODULE_I2C, 0)					/* I2C1 SCL / I2C2 */
+ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0)					/* I2C1 SDA */
+ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0)					/* I2C3 */
+ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0)					/* I2C5 */
+ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0)					/* I2C7 */
+ALTERNATE(PIN_MASK(4, 0x30), 1, MODULE_ADC, 0)					/* ADC0-1 */
+ALTERNATE(PIN_MASK(4, 0x02), 1, MODULE_ADC, 0)					/* ADC4 */
+ALTERNATE(PIN_MASK(F, 0x01), 1, MODULE_ADC, 0)					/* ADC9 */
+ALTERNATE(PIN_MASK(B, 0x80), 1, MODULE_PWM, 0)					/* KB Backlight */
+ALTERNATE(PIN_MASK(C, 0x18), 1, MODULE_PWM, 0) 					/* LED 1 & 2 */
+
+/* Keyboard Pins */
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
+GPIO(KBD_KSO2, PIN(1, 7), GPIO_OUT_LOW)						/* KSO_02 inverted */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
+ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
+
+/* Power Switch Logic (PSL) inputs */
+ALTERNATE(PIN_MASK(0, 0x03), 1, MODULE_PMU, 0)					/* GPIO00, GPIO01 */
+ALTERNATE(PIN_MASK(D, 0x04), 1, MODULE_PMU, 0)					/* GPIOD2 */
diff --git a/board/careena/led.c b/board/careena/led.c
new file mode 100644
index 0000000000..fc6f427cd2
--- /dev/null
+++ b/board/careena/led.c
@@ -0,0 +1,66 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "ec_commands.h"
+#include "led_pwm.h"
+#include "util.h"
+
+const enum ec_led_id supported_led_ids[] = {
+	EC_LED_ID_POWER_LED,
+};
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+/*
+ * We only have a blue and an amber LED, so setting any other colour results in
+ * both LEDs being off.
+ */
+struct pwm_led led_color_map[EC_LED_COLOR_COUNT] = {
+				/* Amber, Blue */
+	[EC_LED_COLOR_RED]    = {   0,   0 },
+	[EC_LED_COLOR_GREEN]  = {   0,   0 },
+	[EC_LED_COLOR_BLUE]   = {   0, 100 },
+	[EC_LED_COLOR_YELLOW] = {   0,   0 },
+	[EC_LED_COLOR_WHITE]  = {   0,   0 },
+	[EC_LED_COLOR_AMBER]  = {  100,  0 },
+};
+
+/* One logical LED with amber and blue channels. */
+struct pwm_led pwm_leds[CONFIG_LED_PWM_COUNT] = {
+	{
+		PWM_CH_LED1_AMBER,
+		PWM_CH_LED2_BLUE,
+		PWM_LED_NO_CHANNEL,
+	},
+};
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	memset(brightness_range, '\0',
+	       sizeof(*brightness_range) * EC_LED_COLOR_COUNT);
+	brightness_range[EC_LED_COLOR_AMBER] = 100;
+	brightness_range[EC_LED_COLOR_BLUE] = 100;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	enum pwm_led_id pwm_id;
+
+	/* Convert ec_led_id to pwm_led_id. */
+	if (led_id == EC_LED_ID_POWER_LED)
+		pwm_id = PWM_LED0;
+	else
+		return EC_ERROR_UNKNOWN;
+
+	if (brightness[EC_LED_COLOR_BLUE])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_BLUE);
+	else if (brightness[EC_LED_COLOR_AMBER])
+		set_pwm_led_color(pwm_id, EC_LED_COLOR_AMBER);
+	else
+		/* Otherwise, the "color" is "off". */
+		set_pwm_led_color(pwm_id, -1);
+
+	return EC_SUCCESS;
+}