nuc: Fixed the bug of i2c caused by writing START bit in SMBCTL1.

In rare case, executing i2c_interrupt function will generate unnecessary
START condition if START bit is 1 in SMBCTL1.

Please see the layout of SMBCTL1 register below.
         Bit [7] - STASTRE
         Bit [6] - NMINTE
         Bit [5] - GCMEN
         Bit [4] - ACK
         Bit [3] - EOBINTE
         Bit [2] - INTEN
         Bit [1] - STOP
         Bit [0] - START

In order to set or clear bits of INTEN and NMINTE, we need to read SMBCTL1,
or the bit2,6 and write back to register. But we will issue unnecessary
START condition if bit 0 is 1. (ie. Start condition is not sent yet)
Then FW will receive unexpected SDAST interrupt and sometime it collapses
state machine when i2c receives NACK condition.

The solution is enabling these two bits in i2c_init_bus function. Using
task_enalble/disable_irq (NVIC register) to enable or disable i2c interrupts
instead.

Modified sources:
1. i2c.c: Fixed the bug of i2c caused by writing START bit in SMBCTL1.
2. i2c.c: Add more debug messages for unexpected bus state.

BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none

Change-Id: I37dbb0e5b61f4a5ba12f0638535f8031522c1711
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/322883
Reviewed-by: Randall Spangler <rspangler@chromium.org>

0 files changed, 0 insertions, 0 deletions