diff options
| author | Wai-Hong Tam <waihong@google.com> | 2020-09-17 14:35:12 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-09-23 19:46:57 +0000 |
| commit | 79de579bf0278a1ab6d8ba6573e70855ec26d687 (patch) | |
| tree | 161ac24e7ddf9823b1df01049198524c5c78075f /board/coachz/gpio.inc | |
| parent | a4e14b97193fe079d18e929ce9d28b586d5418de (diff) | |
| download | chrome-ec-79de579bf0278a1ab6d8ba6573e70855ec26d687.tar.gz | |
Coachz: Implement the base detection
The implementation is based on the poppy reference, with the following
changes:
* Use proper GPIOs and ADC channel
* Not notify ACPI, which is invalid on ARM boards
* Update comments
BRANCH=None
BUG=b:168712053
TEST=Built the Coachz image.
Change-Id: Ie0b0eaf81cdcbd2b2219eef0c895fbd41971d1e4
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2416998
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Diffstat (limited to 'board/coachz/gpio.inc')
| -rw-r--r-- | board/coachz/gpio.inc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/board/coachz/gpio.inc b/board/coachz/gpio.inc index 128620d949..d60d49fd77 100644 --- a/board/coachz/gpio.inc +++ b/board/coachz/gpio.inc @@ -39,6 +39,8 @@ GPIO_INT(POWER_GOOD, PIN(5, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, chipset_p GPIO_INT(WARM_RESET_L, PIN(F, 4), GPIO_INT_BOTH | GPIO_SEL_1P8V, chipset_warm_reset_interrupt) /* AP warm reset */ GPIO_INT(AP_EC_SPI_CS_L, PIN(5, 3), GPIO_INT_FALLING | GPIO_PULL_DOWN, shi_cs_event) /* EC SPI Chip Select */ +GPIO_INT(BASE_DET_L, PIN(3, 7), GPIO_INT_BOTH, base_detect_interrupt) /* Detachable base attached? */ + /* Sensor interrupts */ GPIO_INT(ACCEL_GYRO_INT_L, PIN(A, 0), GPIO_INT_FALLING | GPIO_SEL_1P8V, bmi160_interrupt) /* Accelerometer/gyro interrupt */ @@ -85,9 +87,7 @@ GPIO(WLC_IRQ_CONN, PIN(7, 4), GPIO_INPUT) GPIO(WLC_NRST_CONN, PIN(C, 5), GPIO_INPUT) /* Base detection */ -/* TODO(b/168712053): Implement the base detection */ -GPIO(BASE_DET_L, PIN(3, 7), GPIO_INPUT) -GPIO(EN_BASE, PIN(0, 4), GPIO_INPUT) +GPIO(EN_BASE, PIN(0, 4), GPIO_OUT_LOW) /* Enable power to detachable base */ /* USB-C */ GPIO(USB_C0_PD_RST_L, PIN(F, 1), GPIO_ODR_HIGH) /* Port-0 TCPC chip reset, actaully Open-Drain */ @@ -149,6 +149,7 @@ ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0) /* I2C1 SCL (GPIO87) ALTERNATE(PIN_MASK(3, 0x48), 1, MODULE_I2C, 0) /* I2C5 (GPIO33/36) */ ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, GPIO_SEL_1P8V) /* I2C7 (GPIOB2/B3) - 1.8V */ ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0) /* I2C3 (GPIOD0/D1) */ +ALTERNATE(PIN_MASK(3, 0x80), 0, MODULE_ADC, 0) /* ADC5 (GPIO37) */ ALTERNATE(PIN_MASK(4, 0x1C), 0, MODULE_ADC, 0) /* ADC1 (GPIO44), ADC2 (GPIO43), ADC3 (GPIO42) */ ALTERNATE(PIN_MASK(4, 0xC0), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SDO (GPIO47), SHI_SDI (GPIO46) */ ALTERNATE(PIN_MASK(5, 0x28), 1, MODULE_SPI, GPIO_SEL_1P8V) /* SHI_SCLK (GPIO55), SHI_CS# (GPIO53) */ |