diff options
| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2019-05-30 16:25:15 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-06-13 23:02:44 +0000 |
| commit | 8ca44cb4eca69d44e9fce0b93b58be9c7d9d19f3 (patch) | |
| tree | 4913ea0403d24fc4574bfa2941ee4de7e28a000c /board/coral/gpio.inc | |
| parent | 037eb91f65510d2949289f837c716b7fa997746f (diff) | |
| download | chrome-ec-8ca44cb4eca69d44e9fce0b93b58be9c7d9d19f3.tar.gz | |
intel_x86/power: Consolidate chipset specific power signals array
Currently chipset specific power signals are defined at board/baseboard
level. These power signals are moved to chipset specific file to minimize
the redundant power signals array defined for each board/baseboard.
BUG=b:134079574
BRANCH=none
TEST=make buildall -j
Change-Id: I351904f7cd2e0f27844c0711beb118d390219581
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636837
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'board/coral/gpio.inc')
| -rw-r--r-- | board/coral/gpio.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/coral/gpio.inc b/board/coral/gpio.inc index a4f236a22c..43a130a140 100644 --- a/board/coral/gpio.inc +++ b/board/coral/gpio.inc @@ -23,7 +23,7 @@ GPIO_INT(PCH_SLP_S0_L, PIN(7, 5), GPIO_INT_BOTH, power_signal_interrupt) /* #endif GPIO_INT(PCH_SLP_S4_L, PIN(8, 6), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S4_L */ GPIO_INT(PCH_SLP_S3_L, PIN(7, 3), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S3_L */ -GPIO_INT(SUSPWRNACK, PIN(7, 2), GPIO_INT_BOTH, power_signal_interrupt) +GPIO_INT(SUSPWRDNACK, PIN(7, 2), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(RSMRST_L_PGOOD, PIN(6, 0), GPIO_INT_BOTH, power_signal_interrupt) /* PMIC_EC_RSMRST_ODL */ GPIO_INT(ALL_SYS_PGOOD, PIN(5, 0), GPIO_INT_BOTH, power_signal_interrupt) /* PMIC_EC_PWROK_OD */ |