diff options
author | Vadim Bendebury <vbendeb@chromium.org> | 2018-09-25 18:15:56 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2018-11-05 22:09:19 -0800 |
commit | 7ba4e5f6cb3d96eb93b6aad45bb28cb2e9f06d1d (patch) | |
tree | 6885ee87f3a7e993353655903a7b998013a092de /board/cr50/board.c | |
parent | c6f536334535887c6ef95ae1432b79b816ea86b9 (diff) | |
download | chrome-ec-7ba4e5f6cb3d96eb93b6aad45bb28cb2e9f06d1d.tar.gz |
cr50: enable ITE CCD programming
This patch enables support of ITE EC programming by Cr50. ITE EC sync
sequence generator implementation is being added to the image, I2C RX
and TX queue sizes are increased to be able to accommodate messages
sent during programming session.
Board level callback function is provided to request ITE SYNC sequence
generation on the next boot, and to reset the H1 with a 10 ms delay,
necessary for CCD host USB communications to quiesce.
Board startup code is modified to when requested invoke function
generating ITE SYNC sequence early in the boot before jitter
configuration is locked.
BRANCH=cr50, cr50-mp
BUG=b:75976718
TEST=with the rest of the patches applied verified that it is possible
to disable and re-enable clock jitter at run time.
Change-Id: I88367b200ceb5b62613f96061d565faa56f4d75a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1263898
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Diffstat (limited to 'board/cr50/board.c')
-rw-r--r-- | board/cr50/board.c | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/board/cr50/board.c b/board/cr50/board.c index 3059a4ab9d..1ba863e9ac 100644 --- a/board/cr50/board.c +++ b/board/cr50/board.c @@ -14,6 +14,7 @@ #include "flash.h" #include "flash_config.h" #include "gpio.h" +#include "ite_sync.h" #include "hooks.h" #include "i2c.h" #include "i2cs.h" @@ -620,6 +621,27 @@ static void check_board_id_mismatch(void) system_reset(0); } +/* + * Check if ITE SYNC sequence generation was requested before the reset, if so + * - clear the request and call the function to generate the sequence. + */ +static void maybe_trigger_ite_sync(void) +{ + uint32_t lls1; + + lls1 = GREG32(PMU, LONG_LIFE_SCRATCH1); + + if (!(lls1 & BOARD_ITE_EC_SYNC_NEEDED)) + return; + + /* Clear the sync required bit, this should work only once. */ + GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG1, 1); + GREG32(PMU, LONG_LIFE_SCRATCH1) = lls1 & ~BOARD_ITE_EC_SYNC_NEEDED; + GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG1, 0); + + generate_ite_sync(); +} + /* Initialize board. */ static void board_init(void) { @@ -639,6 +661,7 @@ static void board_init(void) init_pmu(); reset_wake_logic(); init_trng(); + maybe_trigger_ite_sync(); init_jittery_clock(1); init_runlevel(PERMISSION_MEDIUM); /* Initialize NvMem partitions */ @@ -1520,3 +1543,26 @@ static int command_rollback(int argc, char **argv) DECLARE_CONSOLE_COMMAND(rollback, command_rollback, "", "Force rollback to escape DEV image."); #endif + +/* + * Set long life register bit requesting generating of the ITE SYNC sequence + * and reboot. + */ +static void deferred_ite_sync_reset(void) +{ + /* Enable writing to the long life register */ + GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG1, 1); + GREG32(PMU, LONG_LIFE_SCRATCH1) |= BOARD_ITE_EC_SYNC_NEEDED; + /* Disable writing to the long life register */ + GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG1, 0); + + system_reset(SYSTEM_RESET_MANUALLY_TRIGGERED | + SYSTEM_RESET_HARD); +} +DECLARE_DEFERRED(deferred_ite_sync_reset); + +void board_start_ite_sync(void) +{ + /* Let the usb reply to make it to the host. */ + hook_call_deferred(&deferred_ite_sync_reset_data, 10 * MSEC); +} |