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| author | Mary Ruthven <mruthven@chromium.org> | 2017-01-18 14:51:05 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-01-20 02:01:17 -0800 |
| commit | 423eac3ac1dc2e01aac290f7799205a114107171 (patch) | |
| tree | e52bcbdf47a56d5bb035cbd9b6cbbbe05c6ac7a2 /board/cr50/board.c | |
| parent | 767a12c659e9ff03053ad2f691094d9efeb9e5e6 (diff) | |
| download | chrome-ec-423eac3ac1dc2e01aac290f7799205a114107171.tar.gz | |
cr50: decrease sleep delay to 20 seconds after init and resumestabilize-fsi-9202.5.0.Bstabilize-fsi-9202.10.Bstabilize-M57-9202.35.0.Bstabilize-9202.Bstabilize-9202.64.Bstabilize-9202.56.Bstabilize-9202.28.Bstabilize-9202.18.Brelease-R57-9202.B
3 minutes is too long to delay sleep after init and resume from wake
pin. This change decreases the delay to 20 seconds
BUG=none
BRANCH=none
TEST=manual
Use the cr50 power consumption to verify the sleep state
active 50mW
sleep 7mW
deep sleep 1mW
make sure suzyq is disconnected
use uart to reboot cr50
run 'reboot ap-off' on the EC console
make sure cr50 enters deep sleep at second 20
use uart to wakeup cr50 make sure it stays awake for 20 seconds
and then enters deep sleep.
wake it up again using uart and run 'idle s'
verify it enters regular sleep after 20 seconds
use uart to wake it up, make sure it does a regular sleep resume
and then goes back into regular sleep after 20 seconds
Change-Id: I65791bd3d915ceda11dc29b74e150ba589f2fa9e
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430388
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Diffstat (limited to 'board/cr50/board.c')
| -rw-r--r-- | board/cr50/board.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/cr50/board.c b/board/cr50/board.c index fe23db81de..4c56281dbb 100644 --- a/board/cr50/board.c +++ b/board/cr50/board.c @@ -290,7 +290,7 @@ void pmu_wakeup_interrupt(void) * Delay sleep long enough for a SPI slave transaction to start * or for the system to be reset. */ - delay_sleep_by(3 * MINUTE); + delay_sleep_by(20 * SECOND); /* * If sys_rst_l or plt_rst_l (if signal is present) is |