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| author | Mary Ruthven <mruthven@google.com> | 2019-01-28 18:10:24 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-02-01 15:19:33 -0800 |
| commit | 9bf849c6982b32836f0d6d447b055431e42be462 (patch) | |
| tree | a0bde09a4191bb2100603d86691323459a5f2051 /board/cr50/board.c | |
| parent | 98e568636f0ec744b3684466695cd3b1da68aead (diff) | |
| download | chrome-ec-9bf849c6982b32836f0d6d447b055431e42be462.tar.gz | |
cr50: change EC_TX_CR50_RX gpio
The interrupt gpios are all grouped at the top of gpio.inc. They start
using PIN(1, 0) and use the next pin as interrupts are added.
EC_TX_CR50_RX used to be a standard interrupt, but we stopped using the
interrupt handler in chip/g/gpio.c and started using a dedicated
interrupt for this signal, so we could do uart bitbang faster. This
change moves EC_TX_CR50_RX, so we can keep the standard we were using
for interrupt definitions. It moves EC_TX_CR50_RX to PIN(1, 11,)
because that's the highest unused pin. We should be able to continue
counting up for interrupt definitions and counting down for other gpio
definitions.
BUG=none
BRANCH=cr50
TEST=use uart bitbang to program nocturne.
Change-Id: I46c1b296db57d774203ba097cc82722f31388d0b
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1443870
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Diffstat (limited to 'board/cr50/board.c')
| -rw-r--r-- | board/cr50/board.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/board/cr50/board.c b/board/cr50/board.c index ef6ea35ded..20c5de0030 100644 --- a/board/cr50/board.c +++ b/board/cr50/board.c @@ -97,7 +97,7 @@ struct uart_bitbang_properties bitbang_config = { .uart = UART_EC, .tx_gpio = GPIO_DETECT_SERVO, /* This is TX to EC console. */ .rx_gpio = GPIO_EC_TX_CR50_RX, - .rx_irq = GC_IRQNUM_GPIO1_GPIO4INT, /* Must match gpoi.inc */ + .rx_irq = GC_IRQNUM_GPIO1_GPIO11INT, /* Must match gpoi.inc */ /* * The rx/tx_pinmux_regval values MUST agree with the pin config for * both the TX and RX GPIOs in gpio.inc. Don't change one without @@ -106,10 +106,10 @@ struct uart_bitbang_properties bitbang_config = { .tx_pinmux_reg = GBASE(PINMUX) + GOFFSET(PINMUX, DIOB5_SEL), .tx_pinmux_regval = GC_PINMUX_GPIO1_GPIO3_SEL, .rx_pinmux_reg = GBASE(PINMUX) + GOFFSET(PINMUX, DIOB6_SEL), - .rx_pinmux_regval = GC_PINMUX_GPIO1_GPIO4_SEL, + .rx_pinmux_regval = GC_PINMUX_GPIO1_GPIO11_SEL, }; -DECLARE_IRQ(GC_IRQNUM_GPIO1_GPIO4INT, uart_bitbang_irq, 0); +DECLARE_IRQ(GC_IRQNUM_GPIO1_GPIO11INT, uart_bitbang_irq, 0); const char *device_state_names[] = { "init", |