cr50: allow board to provide flash configuration

The g chip is used in multiple designs, likely to have different flash
memory layout and access permissions.

This patch introduces a mechanism which allows the board layer to
provide flash configuration information to the flash driver.

The flash region which is going to be enabled for write access depends
on the area the code is executing from. If running from the bottom
half (A), the whole top half should be writeable (this includes both
NVRAM area and the B code space). If running from B, the writeable
area starts on top of RO and extends to the end of NVRAM.

CQ-DEPEND=CL:*248190
BRANCH=none
BUG=chrome-os-partner:37754
TEST=with the rest of the patches applied verified that software
     update can happen in both spaces, A and B.

Change-Id: Iab1c1a2766ae9bcfe04ff170c010f180cd1f770f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/327412
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Nadim Taha <ntaha@chromium.org>

1 files changed, 35 insertions, 0 deletions

diff --git a/board/cr50/board.c b/board/cr50/board.c
index 492989b4f1..3b754655b8 100644
--- a/board/cr50/board.c
+++ b/board/cr50/board.c
@@ -6,6 +6,7 @@
 #include "common.h"
 #include "console.h"
 #include "ec_version.h"
+#include "flash_config.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "registers.h"
@@ -160,3 +161,37 @@ const void * const usb_strings[] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
 #endif
+
+int flash_regions_to_enable(struct g_flash_region *regions,
+			    int max_regions)
+{
+	uint32_t half = CONFIG_FLASH_SIZE / 2;
+
+	if (max_regions < 1)
+		return 0;
+
+	if ((uint32_t)flash_regions_to_enable <
+	    (CONFIG_MAPPED_STORAGE_BASE + half))
+		/*
+		 * Running from RW_A. Need to enable writes into the top half,
+		 * which consists of NV_RAM and RW_B sections.
+		 */
+		regions->reg_base = CONFIG_MAPPED_STORAGE_BASE + half;
+	else
+		/*
+		 * Running from RW_B, need to enable access to both program
+		 * memory in the lower half and the NVRAM space in the top
+		 * half.
+		 *
+		 * NVRAM space in the top half by design is at the same offset
+		 * and of the same size as the RO section in the lower half.
+		 */
+		regions->reg_base = CONFIG_MAPPED_STORAGE_BASE +
+			CONFIG_RO_SIZE;
+
+	/* The size of the write enable area is the same in both cases. */
+	regions->reg_size = half;
+	regions->reg_perms =  FLASH_REGION_EN_ALL;
+
+	return 1; /* One region is enough. */
+}