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authorVadim Bendebury <vbendeb@chromium.org>2021-06-18 11:27:23 -0700
committerCommit Bot <commit-bot@chromium.org>2021-06-25 20:57:56 +0000
commitc6095192742c9f59f72a6178ece5a2dd8cea4e43 (patch)
tree231827d025fd8a333ffb02249aee9960ae19a701 /board/cr50/board.h
parenta6e62a3020e1f6d53880d91760073c4f91a63bef (diff)
downloadchrome-ec-c6095192742c9f59f72a6178ece5a2dd8cea4e43.tar.gz
To be able to send and receive multiple SPI buffer quantities in a single SPI transaction it is necessary to control the SPI CS signal directly, as opposed to connecting it to the SPI controller. Direct mode allows to keep CS asserted as long as necessary to transfer the full data blob, size of which might exceed the the size of the SPI controller buffer. BUG=b:79492818 TEST=flashrom access still works fine: $ flashrom -p raiden_debug_spi:target=ap --flash-name flashrom f10dff7b-dirty on Linux 5.4.0-71-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Raiden target: 2 Found GigaDevice flash chip "GD25Q127C/GD25Q128C" (16384 kB, SPI) on... vendor="GigaDevice" name="GD25Q127C/GD25Q128C" Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Idecf019d3fd19675d7f78e4dc1140106a2112c6b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2973580 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Diffstat (limited to 'board/cr50/board.h')
-rw-r--r--board/cr50/board.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/board/cr50/board.h b/board/cr50/board.h
index 1e83a30340..06e1252101 100644
--- a/board/cr50/board.h
+++ b/board/cr50/board.h
@@ -137,7 +137,6 @@
/* Enable SPI controller (SPI) module */
#define CONFIG_SPI_CONTROLLER
-#define CONFIG_SPI_CONTROLLER_NO_CS_GPIOS
#define CONFIG_SPI_CONTROLLER_CONFIGURE_GPIOS
#define CONFIG_SPI_FLASH_PORT 0