diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2016-12-19 16:55:12 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-12-20 21:56:41 -0800 |
| commit | 9cc53cb892ca53f600235241b3f0ddcdeea09da6 (patch) | |
| tree | 7e761cbcfc61b984fd7e68c1ba3c5861076fbc16 /board/cr50/rdd.c | |
| parent | 68ce71d642e7c8fa612b03799a91e3982e8c9854 (diff) | |
| download | chrome-ec-9cc53cb892ca53f600235241b3f0ddcdeea09da6.tar.gz | |
cr50: keep board properties related code in board.c
There are plans to extend use of the LONG_LIFE_SCRATCH1 register for
other purposes than keeping board properties. Just as the board
properties, the new use is also very board specific. This patch moves
the board properties code from chip/g to board/cr50, where it belongs.
Instead of reading board properties bitmap and checking if various
bits are set, api functions are now provided to allow determining
various properties settings without actually looking at the properties
bitmap.
CQ-DEPEND=CL:*313057
BRANCH=none
BUG=chrome-os-partner:58961
TEST=verified that both Gru and Reef boot with the new image,
additionally, on Reef confirmed that it is possible to
communicate with the H1 over USB, and that plt_reset signal is
handled properly.
Change-Id: Id0dd2dc16389f773a149fb01eee1ce7bb99c4547
Reviewed-on: https://chromium-review.googlesource.com/422081
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Diffstat (limited to 'board/cr50/rdd.c')
| -rw-r--r-- | board/cr50/rdd.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/board/cr50/rdd.c b/board/cr50/rdd.c index 1275b0dcde..e294d42d5e 100644 --- a/board/cr50/rdd.c +++ b/board/cr50/rdd.c @@ -137,7 +137,6 @@ void rdd_detached(void) void ccd_phy_init(int enable_ccd) { - uint32_t properties = system_get_board_properties(); /* * For boards that have one phy connected to the AP and one to the * external port PHY0 is for the AP and PHY1 is for CCD. @@ -161,10 +160,10 @@ void ccd_phy_init(int enable_ccd) /* * If the board has the non-ccd phy connected to the AP initialize the - * phy no matter what. Otherwise only initialized the phy if ccd is + * phy no matter what. Otherwise only initialize the phy if ccd is * enabled. */ - if ((properties & BOARD_USB_AP) || enable_ccd) { + if (board_has_ap_usb() || enable_ccd) { usb_init(); usb_is_initialized = 1; } @@ -172,8 +171,7 @@ void ccd_phy_init(int enable_ccd) void disable_ap_usb(void) { - if ((system_get_board_properties() & BOARD_USB_AP) && - !ccd_is_enabled() && usb_is_initialized) { + if (board_has_ap_usb() && !ccd_is_enabled() && usb_is_initialized) { usb_release(); usb_is_initialized = 0; } @@ -182,8 +180,7 @@ DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, disable_ap_usb, HOOK_PRIO_DEFAULT); void enable_ap_usb(void) { - if ((system_get_board_properties() & BOARD_USB_AP) && - !ccd_is_enabled() && !usb_is_initialized) { + if (board_has_ap_usb() && !ccd_is_enabled() && !usb_is_initialized) { usb_is_initialized = 1; usb_init(); } |