diff options
| author | Andrey Petrov <andrey.petrov@intel.com> | 2015-04-16 17:25:44 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-04-23 00:13:55 +0000 |
| commit | 279de61f843d6d364c88110d0bb12e91d314f0ba (patch) | |
| tree | 6776857ce6585c7035298544e6a6785ef7fa78ad /board/cyan/lfw | |
| parent | 269c330f0e32a2c26e03fc932f9b02426ee09b79 (diff) | |
| download | chrome-ec-279de61f843d6d364c88110d0bb12e91d314f0ba.tar.gz | |
mec1322: initial version of lfw loader
lfw is a customized boot loader with max targeted code size of 4k
and data size of 2k.It supports minimal functionalities required to
support chromebooks RO/RW architecture.It is placed in the
write porected section with RO image .
Capabilities include SPI,DMA,UART with minimal debugging support.
Currently sysjump support is missing and exception handling is very basic.
BUG=chromium:37510
TEST=make buildall -j, flashing and booting on strago
BRANCH=None
Change-Id: I803998d489297dfe0745dcccbb54412035d73f78
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/265904
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'board/cyan/lfw')
| -rw-r--r-- | board/cyan/lfw/gpio.inc | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/board/cyan/lfw/gpio.inc b/board/cyan/lfw/gpio.inc new file mode 100644 index 0000000000..d1bb19cfcb --- /dev/null +++ b/board/cyan/lfw/gpio.inc @@ -0,0 +1,16 @@ +/* -*- mode:c -*- + * + * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Minimal set of GPIOs needed for LFW loader + */ + +GPIO(PVT_CS0, PORT(14), 6, GPIO_ODR_HIGH) /* SPI PVT Chip select */ + +/* Alternate functions GPIO definition */ +ALTERNATE(PORT(16), 0x24, 1, MODULE_UART, 0) /* UART0 */ +ALTERNATE(PORT(5), 0x10, 1, MODULE_SPI, 0) +ALTERNATE(PORT(16), 0x10, 1, MODULE_SPI, 0) +ALTERNATE(PORT(15), 0x08, 1, MODULE_SPI, 0) /* 153: CLK */ |