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| author | Michael5 Chen <michael5_chen1@pegatron.corp-partner.google.com> | 2020-12-01 12:25:44 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-12-01 08:30:23 +0000 |
| commit | 57ad295fc22a23991ace7610d502c5ff872c998b (patch) | |
| tree | d90c86899a2255c3f79e57a0dc655ad151ff08d9 /board/delbin/board.h | |
| parent | 71def4658cb07a00e00f515622500051c2557fde (diff) | |
| download | chrome-ec-57ad295fc22a23991ace7610d502c5ff872c998b.tar.gz | |
delbin: Config EC chipset
Base on DVT schematic, change EC chip to npcx7m7fc from npcx7m6fc.
BUG=b:174106425
BRANCH=firmware-volteer-13521.B
TEST=bring-up
Signed-off-by: Michael5 Chen <michael5_chen1@pegatron.corp-partner.google.com>
Change-Id: I7c1b7a3a39dc4dd4bacbd23b468a6515c0b04eb9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2567080
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Diffstat (limited to 'board/delbin/board.h')
| -rw-r--r-- | board/delbin/board.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/board/delbin/board.h b/board/delbin/board.h index 0b8278d867..df499eeffc 100644 --- a/board/delbin/board.h +++ b/board/delbin/board.h @@ -11,6 +11,12 @@ /* Baseboard features */ #include "baseboard.h" +/* + * The RAM and flash size combination on the NPCX797FC dose not leave + * any unused flash space that can be used to store the .init_rom section. + */ +#undef CONFIG_CHIP_INIT_ROM_REGION + #undef NPCX_PWM1_SEL #define NPCX_PWM1_SEL 0 /* GPIO C2 is not used as PWM1. */ |