dingdong: Initial board and USB PD support.

Allows dingdong to receive initial USB PD communication (source
capabilities payload) and with some manual manipulation (see 'TEST=')
drive DPout.

CL is based heavily off hoho dongle where all files were copied from
   board/hoho:
     7b1e58c ectool: Add host command support to set fan RPM for each
             fan separately

   Files gpio.inc, board.h & board.c were modified but others should
   be identical.

BRANCH=none
BUG=chrome-os-partner:31193
TEST=manual,

When attaching dingdong to samus_pd and configured via
  'pd dualrole source'

I see following on samus_pd console:
    C1 st9
    Switch to 5000 V 900 mA (for 900/900 mA)
    C1 st10
    C1 st11
    C1 st12

showing power constract and transition to SRC_RDY:
    > pd 1 state
    Port C1, Enabled - Role: SRC Polarity: CC1 State: SRC_READY

    > typec 1 dp

Also if I connect in CC1 configuration and get access to dingdong
console I can
   > gpioset PD_SBU_ENABLE 1

And see dingdong drive external monitor

Change-Id: I30ef6f8503a3fb015cfb8806bc36fb98f5150e40
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221913
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>

1 files changed, 30 insertions, 0 deletions

diff --git a/board/dingdong/board.c b/board/dingdong/board.c
new file mode 100644
index 0000000000..70720171a1
--- /dev/null
+++ b/board/dingdong/board.c
@@ -0,0 +1,30 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Dingdong dongle configuration */
+
+#include "adc.h"
+#include "adc_chip.h"
+#include "common.h"
+#include "gpio.h"
+#include "registers.h"
+#include "util.h"
+
+#include "gpio_list.h"
+
+/* Initialize board. */
+void board_config_pre_init(void)
+{
+	/* enable SYSCFG clock */
+	STM32_RCC_APB2ENR |= 1 << 0;
+	/* Remap USART DMA to match the USART driver */
+	STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */
+}
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
+	[ADC_CH_CC1_PD] = {"USB_C_CC1_PD", 3300, 4096, 0, STM32_AIN(1)},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);