diff options
| author | Diana Z <dzigterman@chromium.org> | 2021-06-16 15:31:56 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-06-17 18:07:37 +0000 |
| commit | 622bde78f5064f76d83b1e2c6bad10b3604d7066 (patch) | |
| tree | 8abf052a2ffc405e8e73d8c254de1f04b3cb99b9 /board/dirinboz | |
| parent | 889ce584d36a7a4f271340c9edf6a7d49c104585 (diff) | |
| download | chrome-ec-622bde78f5064f76d83b1e2c6bad10b3604d7066.tar.gz | |
Zork: Update TCPC reset functions to notify NCT38xx driver
The NCT38xx driver is now storing boot information which should be
cleared whenever the TCPC is forcibly reset through the reset line. Add
these reset calls to all zork boards.
BRANCH=None
BUG=None
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I89089a32d4d17dc260df7928028c2dc5fef45aa2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2965846
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Diffstat (limited to 'board/dirinboz')
| -rw-r--r-- | board/dirinboz/board.c | 29 |
1 files changed, 18 insertions, 11 deletions
diff --git a/board/dirinboz/board.c b/board/dirinboz/board.c index 0ee6b94d05..1daf425b2a 100644 --- a/board/dirinboz/board.c +++ b/board/dirinboz/board.c @@ -368,27 +368,34 @@ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { }; BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT); -static void reset_pd_port(int port, enum gpio_signal reset_gpio_l, - int hold_delay, int finish_delay) +static void reset_nct38xx_port(int port) { + enum gpio_signal reset_gpio_l; + + if (port == USBC_PORT_C0) + reset_gpio_l = GPIO_USB_C0_TCPC_RST_L; + else if (port == USBC_PORT_C1) + reset_gpio_l = GPIO_USB_C1_TCPC_RST_L; + else + /* Invalid port: do nothing */ + return; + gpio_set_level(reset_gpio_l, 0); - msleep(hold_delay); + msleep(NCT38XX_RESET_HOLD_DELAY_MS); gpio_set_level(reset_gpio_l, 1); - if (finish_delay) - msleep(finish_delay); + nct38xx_reset_notify(port); + if (NCT38XX_RESET_POST_DELAY_MS != 0) + msleep(NCT38XX_RESET_POST_DELAY_MS); } + void board_reset_pd_mcu(void) { /* Reset TCPC0 */ - reset_pd_port(USBC_PORT_C0, GPIO_USB_C0_TCPC_RST_L, - NCT38XX_RESET_HOLD_DELAY_MS, - NCT38XX_RESET_POST_DELAY_MS); + reset_nct38xx_port(USBC_PORT_C0); /* Reset TCPC1 */ - reset_pd_port(USBC_PORT_C1, GPIO_USB_C1_TCPC_RST_L, - NCT38XX_RESET_HOLD_DELAY_MS, - NCT38XX_RESET_POST_DELAY_MS); + reset_nct38xx_port(USBC_PORT_C1); } uint16_t tcpc_get_alert_status(void) |