diff options
| author | Steven Jian <steven.jian@intel.com> | 2015-04-01 01:25:42 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-05-27 03:58:16 +0000 |
| commit | 937cc8a64e5971def21303e7a19a4ad9553e0ace (patch) | |
| tree | 321543152e0c4d61e686ca7b92edd0d027bb168b /board/discovery-stm32f072 | |
| parent | e216906c9327655d71b8758b7f11c2f744e55018 (diff) | |
| download | chrome-ec-937cc8a64e5971def21303e7a19a4ad9553e0ace.tar.gz | |
mec1322: Simplify GPIO lists
Our existing GPIO macros use port# / gpio#, but the concept of different
GPIO ports does not exist on the mec1322. Therefore, add new GPIO macros
for chips which do not have distinct GPIO ports.
BUG=None
BRANCH=None
TEST=make buildall -j
Change-Id: Ibda97c6563ad447d16dab39ecadab43ccb25174b
Signed-off-by: Steven Jian <steven.jian@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/262841
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Diffstat (limited to 'board/discovery-stm32f072')
| -rw-r--r-- | board/discovery-stm32f072/gpio.inc | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/board/discovery-stm32f072/gpio.inc b/board/discovery-stm32f072/gpio.inc index 63735399f6..6f9e5a2dc5 100644 --- a/board/discovery-stm32f072/gpio.inc +++ b/board/discovery-stm32f072/gpio.inc @@ -6,26 +6,26 @@ */ /* Inputs with interrupt handlers are first for efficiency */ -GPIO_INT(USER_BUTTON, A, 0, GPIO_INT_FALLING, button_event) +GPIO_INT(USER_BUTTON, PIN(A, 0), GPIO_INT_FALLING, button_event) /* Outputs */ -GPIO(LED_U, C, 6, GPIO_OUT_LOW) -GPIO(LED_D, C, 7, GPIO_OUT_LOW) -GPIO(LED_L, C, 8, GPIO_OUT_LOW) -GPIO(LED_R, C, 9, GPIO_OUT_LOW) +GPIO(LED_U, PIN(C, 6), GPIO_OUT_LOW) +GPIO(LED_D, PIN(C, 7), GPIO_OUT_LOW) +GPIO(LED_L, PIN(C, 8), GPIO_OUT_LOW) +GPIO(LED_R, PIN(C, 9), GPIO_OUT_LOW) /* Flash SPI interface */ -GPIO(SPI_WP, C, 3, GPIO_OUT_HIGH) -GPIO(SPI_HOLD, C, 4, GPIO_OUT_HIGH) -GPIO(SPI_CS, B, 12, GPIO_OUT_HIGH) +GPIO(SPI_WP, PIN(C, 3), GPIO_OUT_HIGH) +GPIO(SPI_HOLD, PIN(C, 4), GPIO_OUT_HIGH) +GPIO(SPI_CS, PIN(B, 12), GPIO_OUT_HIGH) -ALTERNATE(B, 0xE000, 0, MODULE_SPI_MASTER, 0) +ALTERNATE(PIN_MASK(B, 0xE000), 0, MODULE_SPI_MASTER, 0) /* Unimplemented signals which we need to emulate for now */ UNIMPLEMENTED(ENTERING_RW) UNIMPLEMENTED(WP_L) -ALTERNATE(A, 0x0600, 1, MODULE_USART, 0) /* USART1: PA09/PA10 */ -ALTERNATE(A, 0xC000, 1, MODULE_UART, 0) /* USART2: PA14/PA15 */ -ALTERNATE(B, 0x0C00, 1, MODULE_USART, 0) /* USART3: PB10/PB11 */ -ALTERNATE(C, 0x0C00, 1, MODULE_USART, 0) /* USART4: PC10/PC11 */ +ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_USART, 0) /* USART1: PA09/PA10 */ +ALTERNATE(PIN_MASK(A, 0xC000), 1, MODULE_UART, 0) /* USART2: PA14/PA15 */ +ALTERNATE(PIN_MASK(B, 0x0C00), 1, MODULE_USART, 0) /* USART3: PB10/PB11 */ +ALTERNATE(PIN_MASK(C, 0x0C00), 1, MODULE_USART, 0) /* USART4: PC10/PC11 */ |