diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2012-02-16 02:27:01 +0000 |
|---|---|---|
| committer | Vincent Palatin <vpalatin@chromium.org> | 2012-02-16 02:52:29 +0000 |
| commit | c9cb9bd6f3d8da7400cffd8840f3fbd46512c993 (patch) | |
| tree | a45bae734485feb2a22e0f0c7dbf6e2e04ae0129 /board/discovery/board.c | |
| parent | 4778d823be038848e2d412628c897e7a865af9ba (diff) | |
| download | chrome-ec-c9cb9bd6f3d8da7400cffd8840f3fbd46512c993.tar.gz | |
stm32l: implement gpio_set_alternate_function
Allow to set easily the SoC pins to one of their native functions.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on Discovery board, check the muxing of the USART pins is still
working and we get traces.
Change-Id: I6e83d2eea8986d814720ad4b2fef588908b99079
Diffstat (limited to 'board/discovery/board.c')
| -rw-r--r-- | board/discovery/board.c | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/board/discovery/board.c b/board/discovery/board.c index 4b4cd676ca..b43e761fc7 100644 --- a/board/discovery/board.c +++ b/board/discovery/board.c @@ -28,16 +28,10 @@ void configure_board(void) #if CONFIG_CONSOLE_UART == 1 /* Select Alternate function for USART1 on pins PA9/PA10 */ - STM32L_GPIO_AFRH(A) = (STM32L_GPIO_AFRH(A) & ~0x00000FF0) | - (0x7 << 8) | (0x7 << 4); - STM32L_GPIO_MODER(A) = (STM32L_GPIO_MODER(A) & ~0x003C0000) | - 0x00280000; + gpio_set_alternate_function(GPIO_A, (1<<9) | (1<<10), GPIO_ALT_USART); #elif CONFIG_CONSOLE_UART == 3 /* Select Alternate function for USART3 on pins PB10/PB11 */ - STM32L_GPIO_AFRH(B) = (STM32L_GPIO_AFRH(B) & ~0x0000FF00) | - (0x7 << 12) | (0x7 << 8); - STM32L_GPIO_MODER(B) = (STM32L_GPIO_MODER(B) & ~0x00F00000) | - 0x00A00000; + gpio_set_alternate_function(GPIO_B, (1<<10) | (1<<11), GPIO_ALT_USART); #endif } |