diff options
| author | Diana Z <dzigterman@chromium.org> | 2020-09-24 10:55:17 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-09-24 20:33:01 +0000 |
| commit | 71b27a53005725f1ec868ea871ad7f46f180ce51 (patch) | |
| tree | 9f3f6c06ec8891393307fc499bc2b56fbc83e196 /board/drawcia/gpio.inc | |
| parent | 1c5511ed5e33231038e019b247df19e1b6178afd (diff) | |
| download | chrome-ec-71b27a53005725f1ec868ea871ad7f46f180ce51.tar.gz | |
Dedede: Remove unnecessary RSMRST_PWRGD_L pull-up
There is an external pull-up on this signal, and so the EC pull-up is
unnecessary and may cause an intermediate voltage when the system enters
G3.
BRANCH=None
BUG=b:169179804
TEST=make -j buildall, boot to S0 on drawlat
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I82a513777018eb9a6cd86450612a5c943d7bd357
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2429385
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'board/drawcia/gpio.inc')
| -rw-r--r-- | board/drawcia/gpio.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/drawcia/gpio.inc b/board/drawcia/gpio.inc index 80b21fa15b..e49b9c6783 100644 --- a/board/drawcia/gpio.inc +++ b/board/drawcia/gpio.inc @@ -14,7 +14,7 @@ GPIO_INT(SLP_S3_L, PIN(H, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt) GPIO_INT(SLP_S0_L, PIN(E, 4), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(SLP_SUS_L, PIN(G, 2), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(VCCIN_AUX_VID0, PIN(D, 0), GPIO_INT_BOTH, power_signal_interrupt) -GPIO_INT(RSMRST_PWRGD_L, PIN(E, 1), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt) +GPIO_INT(RSMRST_PWRGD_L, PIN(E, 1), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(CPU_C10_GATE_L, PIN(G, 1), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(PG_DRAM_OD, PIN(D, 3), GPIO_INT_BOTH, baseboard_all_sys_pgood_interrupt) GPIO_INT(PG_PP1050_ST_OD, PIN(L, 1), GPIO_INT_BOTH, power_signal_interrupt) |