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| author | Koro Chen <koro.chen@mediatek.com> | 2016-05-13 16:01:13 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-05-30 03:55:24 -0700 |
| commit | af0bc62e6721287b2669cb33349e771ab40b89e1 (patch) | |
| tree | e18f579e8dc201280e36a4490df4218bc3d21be0 /board/elm | |
| parent | dc3de2c826fe96c6d45cd72a2135951da4237c74 (diff) | |
| download | chrome-ec-af0bc62e6721287b2669cb33349e771ab40b89e1.tar.gz | |
elm: set SPI2 interface to low in S5
BUG=chrome-os-partner:51708
BRANCH=none
TEST=poweroff elm, measure PP3300 and voltage is ~ 0.05V.
Change-Id: I17088bf15a97eb7337abbe773897eaf298086752
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/344492
Reviewed-by: Rong Chang <rongchang@chromium.org>
Diffstat (limited to 'board/elm')
| -rw-r--r-- | board/elm/board.c | 51 |
1 files changed, 33 insertions, 18 deletions
diff --git a/board/elm/board.c b/board/elm/board.c index 131645b24c..840da0bd8a 100644 --- a/board/elm/board.c +++ b/board/elm/board.c @@ -243,24 +243,6 @@ static void board_init(void) /* Remap SPI2 to DMA channels 6 and 7 */ REG32(STM32_DMA1_BASE + 0xa8) |= (1 << 20) | (1 << 21) | (1 << 24) | (1 << 25); - - /* Enable SPI for KX022 */ - gpio_config_module(MODULE_SPI_MASTER, 1); - - /* Set all four SPI pins to high speed */ - /* pins D0/D1/D3/D4 */ - STM32_GPIO_OSPEEDR(GPIO_D) |= 0x000003cf; - /* pins F6 */ - STM32_GPIO_OSPEEDR(GPIO_F) |= 0x00003000; - - /* Enable clocks to SPI2 module */ - STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2; - - /* Reset SPI2 */ - STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2; - STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2; - - spi_enable(CONFIG_SPI_ACCEL_PORT, 1); } DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); @@ -391,6 +373,24 @@ static void board_chipset_pre_init(void) { /* Enable level shift of AC_OK when power on */ board_extpower_buffer_to_soc(); + + /* Enable SPI for KX022 */ + gpio_config_module(MODULE_SPI_MASTER, 1); + + /* Set all four SPI pins to high speed */ + /* pins D0/D1/D3/D4 */ + STM32_GPIO_OSPEEDR(GPIO_D) |= 0x000003cf; + /* pins F6 */ + STM32_GPIO_OSPEEDR(GPIO_F) |= 0x00003000; + + /* Enable clocks to SPI2 module */ + STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2; + + /* Reset SPI2 */ + STM32_RCC_APB1RSTR |= STM32_RCC_PB1_SPI2; + STM32_RCC_APB1RSTR &= ~STM32_RCC_PB1_SPI2; + + spi_enable(CONFIG_SPI_ACCEL_PORT, 1); } DECLARE_HOOK(HOOK_CHIPSET_PRE_INIT, board_chipset_pre_init, HOOK_PRIO_DEFAULT); @@ -399,6 +399,21 @@ static void board_chipset_shutdown(void) { /* Disable level shift to SoC when shutting down */ gpio_set_level(GPIO_LEVEL_SHIFT_EN_L, 1); + + spi_enable(CONFIG_SPI_ACCEL_PORT, 0); + + /* Disable clocks to SPI2 module */ + STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2; + + gpio_config_module(MODULE_SPI_MASTER, 0); + + /* + * Calling gpio_config_module sets disabled alternate function pins to + * GPIO_INPUT. But to prevent leakage we want to set GPIO_OUT_LOW + */ + gpio_set_flags_by_mask(GPIO_D, 0x1a, GPIO_OUT_LOW); + gpio_set_level(GPIO_SPI2_NSS, 0); + gpio_set_level(GPIO_SPI2_NSS_DB, 0); } DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT); |