diff options
| author | Duncan Laurie <dlaurie@google.com> | 2017-01-17 10:27:29 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-01-18 19:18:57 -0800 |
| commit | 383fea37f6b0240c876cc9a09ff93e405f4632a6 (patch) | |
| tree | a2f4b875009b9094cf849708025262fb2e93cc6d /board/eve/gpio.inc | |
| parent | 268b510f0b981b2bb9d861dce291172687c6a5e5 (diff) | |
| download | chrome-ec-383fea37f6b0240c876cc9a09ff93e405f4632a6.tar.gz | |
eve: Updates from P1 build
- revert the change for issue 61431 as main build systems have
updated resistor values
- enable CONFIG_CHARGER_BD9995X_CHGEN, with the necessary changes
in battery.c to support the custom battery present functions
- enable CONFIG_CHARGER_MAINTAIN_VBAT
- enable CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT for testing
- set pre-charge current to 256mA to better wake up batteries
- set voltage-min to 6.1V to account for charger inaccuracies since
the battery expects >= 6V to wake up
- enable CONFIG_BACKLIGHT_LID to enforce backlight off with lid closed
- put all CONFIG_CMD enables in the same place
- make PCH_ACOK open drain (pull-up to be enabled on PCH)
BUG=chrome-os-partner:61431,chrome-os-partner:61676
BRANCH=none
TEST=manual testing on P1 boards at the factory
Change-Id: Ib20693c8200d253819873d03b54f91e12bda8270
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/428902
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'board/eve/gpio.inc')
| -rw-r--r-- | board/eve/gpio.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/eve/gpio.inc b/board/eve/gpio.inc index f631d2c288..76b86a095a 100644 --- a/board/eve/gpio.inc +++ b/board/eve/gpio.inc @@ -31,7 +31,7 @@ GPIO(WLAN_OFF_L, PIN(7, 2), GPIO_OUT_LOW) /* Disable WLAN */ GPIO(PP3300_DX_WLAN, PIN(A, 7), GPIO_OUT_LOW) /* Enable WLAN 3.3V Power */ GPIO(CHARGER_RST_ODL, PIN(0, 1), GPIO_ODR_HIGH) /* CHARGER_RST_ODL */ GPIO(CPU_PROCHOT, PIN(8, 1), GPIO_OUT_HIGH) /* PROCHOT# to SOC */ -GPIO(PCH_ACOK, PIN(5, 0), GPIO_OUT_LOW) /* ACOK to SOC */ +GPIO(PCH_ACOK, PIN(5, 0), GPIO_ODR_LOW) /* ACOK to SOC */ GPIO(PCH_WAKE_L, PIN(A, 3), GPIO_ODR_HIGH) /* Wake SOC */ GPIO(PCH_RSMRST_L, PIN(7, 0), GPIO_OUT_LOW) /* RSMRST# to SOC */ GPIO(PCH_PWRBTN_L, PIN(4, 1), GPIO_ODR_HIGH) /* Power Button to SOC */ |