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authorGaggery Tsai <gaggery.tsai@intel.com>2017-08-23 09:40:36 +0800
committerchrome-bot <chrome-bot@chromium.org>2017-10-17 13:02:53 -0700
commitf9bd2c554679bc77e4991672997bad7181d6af76 (patch)
tree168f5a74b6a566436139b10df5135dc92daefb34 /board/fizz/gpio.inc
parent9f68af75f6a99134cd03067379d0c1f6a571fe4f (diff)
downloadchrome-ec-f9bd2c554679bc77e4991672997bad7181d6af76.tar.gz
Fizz: enable fan
This patch is to enable fan through PWM4 output and TACH feedback from TA2 GPIOA6, and move EC_PLATFORM_RST to GPIO45. BUG=b:64915426 BRANCH=None TEST=emerge-fizz chromeos-ec and use fanduty and faninfo from EC console to control and check fan status. Probed oscilloscope on PWM output and checked the duty as expected. Made sure the fan was stopped when DUT entered S3 and was running when DUT resumed from S3. Change-Id: I09f3ac43d2e4170b2aff3830f832bc5fd46a15c0 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/627542 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'board/fizz/gpio.inc')
-rw-r--r--board/fizz/gpio.inc4
1 files changed, 3 insertions, 1 deletions
diff --git a/board/fizz/gpio.inc b/board/fizz/gpio.inc
index 6ba6e25523..b50212a17e 100644
--- a/board/fizz/gpio.inc
+++ b/board/fizz/gpio.inc
@@ -33,7 +33,7 @@ GPIO(PCH_ACPRESENT, PIN(5, 0), GPIO_ODR_LOW) /* ACOK to SOC */
GPIO(PCH_WAKE_L, PIN(A, 3), GPIO_ODR_HIGH) /* Wake SOC */
GPIO(PCH_RSMRST_L, PIN(7, 0), GPIO_OUT_LOW) /* RSMRST# to SOC */
GPIO(PCH_PWRBTN_L, PIN(7, 4), GPIO_ODR_HIGH) /* Power Button to SOC */
-GPIO(EC_PLATFORM_RST, PIN(A, 6), GPIO_OUT_LOW) /* EC Reset to LDO_EN */
+GPIO(EC_PLATFORM_RST, PIN(4, 5), GPIO_OUT_LOW) /* EC Reset to LDO_EN */
GPIO(SYS_RESET_L, PIN(6, 1), GPIO_ODR_HIGH) /* Cold Reset to SOC */
GPIO(PMIC_SLP_SUS_L, PIN(8, 5), GPIO_OUT_LOW) /* SLP_SUS# to PMIC */
GPIO(CCD_MODE_ODL, PIN(6, 3), GPIO_INPUT) /* Case Closed Debug Mode */
@@ -101,7 +101,9 @@ ALTERNATE(PIN_MASK(6, 0x30), 1, MODULE_UART, 0) /* GPIO64-65 */ /* UART from E
ALTERNATE(PIN_MASK(8, 0x80), 1, MODULE_I2C, 0) /* GPIO87 */ /* EC_I2C1_3V3_SDA */
ALTERNATE(PIN_MASK(9, 0x01), 1, MODULE_I2C, 0) /* GPIO90 */ /* EC_I2C1_3V3_SCL */
ALTERNATE(PIN_MASK(9, 0x06), 1, MODULE_I2C, 0) /* GPIO91-92 */ /* EC_I2C2_PMIC_3V3_SDA/SCL */
+ALTERNATE(PIN_MASK(A, 0x40), 1, MODULE_PWM, 0) /* GPIOA6 */ /* TACH2 */
ALTERNATE(PIN_MASK(B, 0x30), 1, MODULE_I2C, 0) /* GPIOB4-B5 */ /* EC_I2C0_0_USBC_3V3_SDA/SCL */
+ALTERNATE(PIN_MASK(B, 0x40), 1, MODULE_PWM, 0) /* GPIOB6 */ /* EC_FAN_PWM */
ALTERNATE(PIN_MASK(B, 0x0C), 1, MODULE_I2C, 0) /* GPOPB2-B3 */ /* EC_I2C0_1_3V3_SDA/SCL */
ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0) /* GPIOD0-D1 */ /* EC_I2C3_SENSOR_1V8_SDA/SCL */
/* Alternate functions for LED PWM */