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| author | Furquan Shaikh <furquan@google.com> | 2018-07-17 09:29:52 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-07-18 21:59:00 -0700 |
| commit | 40787b695522e837a8c63a90e02e654dcb6adbd8 (patch) | |
| tree | 503ae06a89ba2dad7976012b7132f17af0e86a61 /board/fleex/gpio.inc | |
| parent | 4afdfbcef0762c59cf0e1a169f2879c9b560fb06 (diff) | |
| download | chrome-ec-40787b695522e837a8c63a90e02e654dcb6adbd8.tar.gz | |
bobba: Change USB2_OTG_ID to open drain
USB2_OTG_ID is 3.3V pin on the EC whereas the SoC expects
USB2_DUALROLE and USB2_VBUS_SNS to be 1.8V. Since there is an
internal pull-up on USB2_DUALROLE from the SoC side, this change
configures USB2_OTG_ID to be open drain so that it is actively
driven from the EC when it wants to pull it low. Otherwise, the
pin would be tri-stated from the EC side allowing it to be pulled
up to 1.8V because of the SoC internal pull-up.
BUG=None
BRANCH=None
TEST=None
Change-Id: Ia7f5cd32a80a2c9d0cc520bbacad0844aaec961d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1140500
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'board/fleex/gpio.inc')
0 files changed, 0 insertions, 0 deletions