diff options
author | YH Lin <yueherngl@chromium.org> | 2022-12-03 00:17:55 +0000 |
---|---|---|
committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-12-05 17:43:18 +0000 |
commit | dd732876495ed4942d00b9f9ca8dd3b01bad7120 (patch) | |
tree | bdff671e5ad3e71e30ab56f4f084f34a2fd72e28 /board/gaelin/usbc_config.c | |
parent | 184d13e77614be3be5374d3fef9d1edf66ec8687 (diff) | |
download | chrome-ec-factory-brya-14909.124.B-main.tar.gz |
Revert "Merge remote-tracking branch cros/main into factory-brya-14909.124.B-main"factory-brya-14909.124.B-main
This reverts commit 184d13e77614be3be5374d3fef9d1edf66ec8687.
Reason for revert: broken build due to ec-utils.
Original change's description:
> Merge remote-tracking branch cros/main into factory-brya-14909.124.B-main
>
> Generated by: util/update_release_branch.py --baseboard brya --relevant_paths_file
> baseboard/brya/relevant-paths.txt factory-brya-14909.124.B-main
>
> Relevant changes:
>
> git log --oneline 19d4d68ffa..aa40b859b3 -- baseboard/brya board/agah
> board/anahera board/banshee board/brya board/crota board/felwinter
> board/gimble board/kano board/mithrax board/osiris board/primus
> board/redrix board/taeko board/taniks board/vell board/volmar
> driver/bc12/pi3usb9201_public.* driver/charger/bq25710.*
> driver/ppc/nx20p348x.* driver/ppc/syv682x_public.*
> driver/retimer/bb_retimer_public.* driver/tcpm/nct38xx.*
> driver/tcpm/ps8xxx_public.* driver/tcpm/tcpci.* include/power/alderlake*
> include/intel_x86.h power/alderlake* power/intel_x86.c
> util/getversion.sh
>
> e6da633c38 driver: Sort header files
> 234a87ae2d tcpci: Add FRS enable to driver structure
> a56be59ccd tcpm_header: add test for tcpm_dump_registers
> 57b3256963 Rename CONFIG_CHARGER_INPUT_CURRENT to _CHARGER_DEFAULT_CURRENT_LIMIT
> e420c8ff9a marasov: Modify TypeC and TypeA configuration.
> 43b53e0045 Add default implementation of board_set_charge_limit
> b75dc90677 Add CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT
> f1b563c350 baseboard: Sort header files
> 7d01b1e58d driver/retimer/ps8818.h: Add I2C ADDR FLAGS 0x30, 0x58, 0x70
> ec31407993 Add CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
> 8f89f69a5b crota: disable lid angle sensor for clamshell
>
> BRANCH=None
> BUG=b:260630630 b:163093572 b:259002141 b:255184961 b:259354679
> BUG=b:247100970 b:254328661
> TEST=`emerge-brya chromeos-ec`
>
> Force-Relevant-Builds: all
> Change-Id: I0ecfa0e6af68631283c7a9e8f1afb9d827176c62
> Signed-off-by: YH Lin <yueherngl@google.com>
Bug: b:260630630 b:163093572 b:259002141 b:255184961 b:259354679
Bug: b:247100970 b:254328661
Change-Id: Ia14942d1bd6a502062399d77cb59d1f4b549b2c9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4077247
Auto-Submit: YH Lin <yueherngl@chromium.org>
Tested-by: YH Lin <yueherngl@chromium.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Commit-Queue: YH Lin <yueherngl@chromium.org>
Diffstat (limited to 'board/gaelin/usbc_config.c')
-rw-r--r-- | board/gaelin/usbc_config.c | 289 |
1 files changed, 215 insertions, 74 deletions
diff --git a/board/gaelin/usbc_config.c b/board/gaelin/usbc_config.c index 98595fc607..806ff2c4ee 100644 --- a/board/gaelin/usbc_config.c +++ b/board/gaelin/usbc_config.c @@ -10,13 +10,17 @@ #include "compile_time_macros.h" #include "console.h" #include "driver/bc12/pi3usb9201_public.h" -#include "driver/ppc/nx20p348x.h" -#include "driver/tcpm/ps8xxx_public.h" +#include "driver/ppc/syv682x_public.h" +#include "driver/retimer/bb_retimer_public.h" +#include "driver/retimer/kb800x.h" +#include "driver/tcpm/nct38xx.h" +#include "driver/tcpm/rt1715.h" #include "driver/tcpm/tcpci.h" #include "ec_commands.h" #include "gpio.h" #include "gpio_signal.h" #include "hooks.h" +#include "ioexpander.h" #include "system.h" #include "task.h" #include "task_id.h" @@ -36,22 +40,29 @@ const struct tcpc_config_t tcpc_config[] = { [USBC_PORT_C0] = { .bus_type = EC_BUS_TYPE_I2C, .i2c_info = { - .port = I2C_PORT_USB_C0_TCPC, - .addr_flags = PS8XXX_I2C_ADDR1_FLAGS, + .port = I2C_PORT_USB_C0_C2_TCPC, + .addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, }, - .drv = &ps8xxx_tcpm_drv, + .drv = &nct38xx_tcpm_drv, .flags = TCPC_FLAGS_TCPCI_REV2_0 | - TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V, + TCPC_FLAGS_NO_DEBUG_ACC_CONTROL, }, [USBC_PORT_C1] = { .bus_type = EC_BUS_TYPE_I2C, .i2c_info = { .port = I2C_PORT_USB_C1_TCPC, - .addr_flags = PS8XXX_I2C_ADDR2_FLAGS, + .addr_flags = RT1715_I2C_ADDR_FLAGS, }, - .drv = &ps8xxx_tcpm_drv, - .flags = TCPC_FLAGS_TCPCI_REV2_0 | - TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V, + .drv = &rt1715_tcpm_drv, + }, + [USBC_PORT_C2] = { + .bus_type = EC_BUS_TYPE_I2C, + .i2c_info = { + .port = I2C_PORT_USB_C0_C2_TCPC, + .addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS, + }, + .drv = &nct38xx_tcpm_drv, + .flags = TCPC_FLAGS_TCPCI_REV2_0, }, }; BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT); @@ -60,16 +71,19 @@ BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT); /* USBC PPC configuration */ struct ppc_config_t ppc_chips[] = { [USBC_PORT_C0] = { - /* Compatible with Silicon Mitus SM5360A */ - .i2c_port = I2C_PORT_USB_C0_PPC, - .i2c_addr_flags = NX20P3483_ADDR2_FLAGS, - .drv = &nx20p348x_drv, + .i2c_port = I2C_PORT_USB_C0_C2_PPC, + .i2c_addr_flags = SYV682X_ADDR0_FLAGS, + .drv = &syv682x_drv, }, [USBC_PORT_C1] = { - /* Compatible with Silicon Mitus SM5360A */ .i2c_port = I2C_PORT_USB_C1_PPC, - .i2c_addr_flags = NX20P3483_ADDR3_FLAGS, - .drv = &nx20p348x_drv, + .i2c_addr_flags = SYV682X_ADDR0_FLAGS, + .drv = &syv682x_drv, + }, + [USBC_PORT_C2] = { + .i2c_port = I2C_PORT_USB_C0_C2_PPC, + .i2c_addr_flags = SYV682X_ADDR2_FLAGS, + .drv = &syv682x_drv, }, }; BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT); @@ -81,100 +95,200 @@ static const struct usb_mux_chain usbc0_tcss_usb_mux = { .mux = &(const struct usb_mux){ .usb_port = USBC_PORT_C0, - .driver = &tcpci_tcpm_usb_mux_driver, - .hpd_update = &ps8xxx_tcpc_update_hpd_status, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, }, }; static const struct usb_mux_chain usbc1_tcss_usb_mux = { .mux = &(const struct usb_mux){ .usb_port = USBC_PORT_C1, - .driver = &tcpci_tcpm_usb_mux_driver, - .hpd_update = &ps8xxx_tcpc_update_hpd_status, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, }, }; +static const struct usb_mux_chain usbc2_tcss_usb_mux = { + .mux = + &(const struct usb_mux){ + .usb_port = USBC_PORT_C2, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, + }, +}; + +struct kb800x_control_t kb800x_control[] = { + [USBC_PORT_C0] = { + }, + [USBC_PORT_C1] = { + .retimer_rst_gpio = GPIO_USB_C1_RT_RST_R_L, + .ss_lanes = { + [KB800X_A0] = KB800X_TX0, [KB800X_A1] = KB800X_RX0, + [KB800X_B0] = KB800X_RX1, [KB800X_B1] = KB800X_TX1, + [KB800X_C0] = KB800X_RX0, [KB800X_C1] = KB800X_TX0, + [KB800X_D0] = KB800X_TX1, [KB800X_D1] = KB800X_RX1, + } + }, + [USBC_PORT_C2] = { + }, +}; +BUILD_ASSERT(ARRAY_SIZE(kb800x_control) == USBC_PORT_COUNT); const struct usb_mux_chain usb_muxes[] = { [USBC_PORT_C0] = { .mux = &(const struct usb_mux) { .usb_port = USBC_PORT_C0, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_USB_C0_C2_MUX, + .i2c_addr_flags = USBC_PORT_C0_BB_RETIMER_I2C_ADDR, }, .next = &usbc0_tcss_usb_mux, }, [USBC_PORT_C1] = { .mux = &(const struct usb_mux) { .usb_port = USBC_PORT_C1, - .driver = &virtual_usb_mux_driver, - .hpd_update = &virtual_hpd_update, + .driver = &kb800x_usb_mux_driver, + .i2c_port = I2C_PORT_USB_C1_MUX, + .i2c_addr_flags = KB800X_I2C_ADDR0_FLAGS, }, .next = &usbc1_tcss_usb_mux, }, + [USBC_PORT_C2] = { + .mux = &(const struct usb_mux) { + .usb_port = USBC_PORT_C2, + .driver = &bb_usb_retimer, + .hpd_update = bb_retimer_hpd_update, + .i2c_port = I2C_PORT_USB_C0_C2_MUX, + .i2c_addr_flags = USBC_PORT_C2_BB_RETIMER_I2C_ADDR, + }, + .next = &usbc2_tcss_usb_mux, + }, }; BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT); /* BC1.2 charger detect configuration */ const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = { [USBC_PORT_C0] = { - .i2c_port = I2C_PORT_USB_C0_BC12, + .i2c_port = I2C_PORT_USB_C0_C2_BC12, .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, }, [USBC_PORT_C1] = { .i2c_port = I2C_PORT_USB_C1_BC12, - .i2c_addr_flags = PI3USB9201_I2C_ADDR_2_FLAGS, + .i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS, + }, + [USBC_PORT_C2] = { + .i2c_port = I2C_PORT_USB_C0_C2_BC12, + .i2c_addr_flags = PI3USB9201_I2C_ADDR_1_FLAGS, }, }; BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT); -static void ps8815_reset(int port) +/* + * USB C0 and C2 uses burnside bridge chips and have their reset + * controlled by their respective TCPC chips acting as GPIO expanders. + * + * ioex_init() is normally called before we take the TCPCs out of + * reset, so we need to start in disabled mode, then explicitly + * call ioex_init(). + */ + +struct ioexpander_config_t ioex_config[] = { + [IOEX_C0_NCT38XX] = { + .i2c_host_port = I2C_PORT_USB_C0_C2_TCPC, + .i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS, + .drv = &nct38xx_ioexpander_drv, + .flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED, + }, + [IOEX_C2_NCT38XX] = { + .i2c_host_port = I2C_PORT_USB_C0_C2_TCPC, + .i2c_addr_flags = NCT38XX_I2C_ADDR2_1_FLAGS, + .drv = &nct38xx_ioexpander_drv, + .flags = IOEX_FLAGS_DEFAULT_INIT_DISABLED, + }, +}; +BUILD_ASSERT(ARRAY_SIZE(ioex_config) == CONFIG_IO_EXPANDER_PORT_COUNT); + +__override int bb_retimer_power_enable(const struct usb_mux *me, bool enable) { - int val; - int i2c_port; - uint16_t i2c_addr_flags; - enum gpio_signal ps8xxx_rst_odl; - - if (port == USBC_PORT_C0) { - ps8xxx_rst_odl = GPIO_USB_C0_RT_RST_L; - i2c_port = I2C_PORT_USB_C0_TCPC; - i2c_addr_flags = PS8XXX_I2C_ADDR1_FLAGS; - } else if (port == USBC_PORT_C1) { - ps8xxx_rst_odl = GPIO_USB_C1_RT_RST_L; - i2c_port = I2C_PORT_USB_C1_TCPC; - i2c_addr_flags = PS8XXX_I2C_ADDR2_FLAGS; + enum ioex_signal rst_signal; + + if (me->usb_port == USBC_PORT_C0) { + rst_signal = IOEX_USB_C0_RT_RST_ODL; + } else if (me->usb_port == USBC_PORT_C2) { + rst_signal = IOEX_USB_C2_RT_RST_ODL; } else { - return; + return EC_ERROR_INVAL; } - gpio_set_level(ps8xxx_rst_odl, 0); - msleep(GENERIC_MAX(PS8XXX_RESET_DELAY_MS, PS8815_PWR_H_RST_H_DELAY_MS)); - gpio_set_level(ps8xxx_rst_odl, 1); - msleep(PS8815_FW_INIT_DELAY_MS); - - CPRINTS("[C%d] %s: patching ps8815 registers", port, __func__); + /* + * We do not have a load switch for the burnside bridge chips, + * so we only need to sequence reset. + */ - if (i2c_read8(i2c_port, i2c_addr_flags, 0x0f, &val) == EC_SUCCESS) - CPRINTS("ps8815: reg 0x0f was %02x", val); - else { - CPRINTS("delay 10ms to make sure ps8815 is waken from idle"); - msleep(10); + if (enable) { + /* + * Tpw, minimum time from VCC to RESET_N de-assertion is 100us. + * For boards that don't provide a load switch control, the + * retimer_init() function ensures power is up before calling + * this function. + */ + ioex_set_level(rst_signal, 1); + /* + * Allow 1ms time for the retimer to power up lc_domain + * which powers I2C controller within retimer + */ + msleep(1); + } else { + ioex_set_level(rst_signal, 0); + msleep(1); } + return EC_SUCCESS; +} - if (i2c_write8(i2c_port, i2c_addr_flags, 0x0f, 0x31) == EC_SUCCESS) - CPRINTS("ps8815: reg 0x0f set to 0x31"); +__override int bb_retimer_reset(const struct usb_mux *me) +{ + /* + * TODO(b/193402306, b/195375738): Remove this once transition to + * QS Silicon is complete + */ + bb_retimer_power_enable(me, false); + msleep(5); + bb_retimer_power_enable(me, true); + msleep(25); - if (i2c_read8(i2c_port, i2c_addr_flags, 0x0f, &val) == EC_SUCCESS) - CPRINTS("ps8815: reg 0x0f now %02x", val); + return EC_SUCCESS; } void board_reset_pd_mcu(void) { - ps8815_reset(USBC_PORT_C0); - usb_mux_hpd_update(USBC_PORT_C0, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); - ps8815_reset(USBC_PORT_C1); - usb_mux_hpd_update(USBC_PORT_C1, USB_PD_MUX_HPD_LVL_DEASSERTED | - USB_PD_MUX_HPD_IRQ_DEASSERTED); + enum gpio_signal tcpc_rst; + + tcpc_rst = GPIO_USB_C0_C2_TCPC_RST_ODL; + + /* + * TODO(b/179648104): figure out correct timing + */ + + gpio_set_level(tcpc_rst, 0); + gpio_set_level(GPIO_USB_C1_RT_RST_R_L, 0); + + /* + * delay for power-on to reset-off and min. assertion time + */ + + msleep(20); + + gpio_set_level(tcpc_rst, 1); + gpio_set_level(GPIO_USB_C1_RT_RST_R_L, 1); + + /* wait for chips to come up */ + + msleep(50); +} + +static void enable_ioex(int ioex) +{ + ioex_init(ioex); } static void board_tcpc_init(void) @@ -182,19 +296,25 @@ static void board_tcpc_init(void) /* Don't reset TCPCs after initial reset */ if (!system_jumped_late()) { board_reset_pd_mcu(); + + /* + * These IO expander pins are implemented using the + * C0/C2 TCPC, so they must be set up after the TCPC has + * been taken out of reset. + */ + enable_ioex(IOEX_C0_NCT38XX); + enable_ioex(IOEX_C2_NCT38XX); } /* Enable PPC interrupts. */ gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL); - gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL); + gpio_enable_interrupt(GPIO_USB_C2_PPC_INT_ODL); /* Enable TCPC interrupts. */ - gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL); - gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL); + gpio_enable_interrupt(GPIO_USB_C0_C2_TCPC_INT_ODL); - /* Enable BC1.2 interrupts. */ - gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL); - gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL); + gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL); + gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL); } DECLARE_HOOK(HOOK_INIT, board_tcpc_init, HOOK_PRIO_INIT_CHIPSET); @@ -202,8 +322,8 @@ uint16_t tcpc_get_alert_status(void) { uint16_t status = 0; - if (gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL) == 0) - status |= PD_STATUS_TCPC_ALERT_0; + if (gpio_get_level(GPIO_USB_C0_C2_TCPC_INT_ODL) == 0) + status |= PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_2; if (gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL) == 0) status |= PD_STATUS_TCPC_ALERT_1; @@ -217,13 +337,15 @@ int ppc_get_alert_status(int port) return gpio_get_level(GPIO_USB_C0_PPC_INT_ODL) == 0; else if (port == USBC_PORT_C1) return gpio_get_level(GPIO_USB_C1_PPC_INT_ODL) == 0; + else if (port == USBC_PORT_C2) + return gpio_get_level(GPIO_USB_C2_PPC_INT_ODL) == 0; return 0; } void tcpc_alert_event(enum gpio_signal signal) { switch (signal) { - case GPIO_USB_C0_TCPC_INT_ODL: + case GPIO_USB_C0_C2_TCPC_INT_ODL: schedule_deferred_pd_interrupt(USBC_PORT_C0); break; case GPIO_USB_C1_TCPC_INT_ODL: @@ -243,6 +365,9 @@ void bc12_interrupt(enum gpio_signal signal) case GPIO_USB_C1_BC12_INT_ODL: usb_charger_task_set_event(1, USB_CHG_EVENT_BC12); break; + case GPIO_USB_C2_BC12_INT_ODL: + usb_charger_task_set_event(2, USB_CHG_EVENT_BC12); + break; default: break; } @@ -252,10 +377,13 @@ void ppc_interrupt(enum gpio_signal signal) { switch (signal) { case GPIO_USB_C0_PPC_INT_ODL: - nx20p348x_interrupt(USBC_PORT_C0); + syv682x_interrupt(USBC_PORT_C0); break; case GPIO_USB_C1_PPC_INT_ODL: - nx20p348x_interrupt(USBC_PORT_C1); + syv682x_interrupt(USBC_PORT_C1); + break; + case GPIO_USB_C2_PPC_INT_ODL: + syv682x_interrupt(USBC_PORT_C2); break; default: break; @@ -273,3 +401,16 @@ __override bool board_is_dts_port(int port) { return port == USBC_PORT_C0; } + +__override bool board_is_tbt_usb4_port(int port) +{ + return true; +} + +__override enum tbt_compat_cable_speed board_get_max_tbt_speed(int port) +{ + if (!board_is_tbt_usb4_port(port)) + return TBT_SS_RES_0; + + return TBT_SS_TBT_GEN3; +} |